7 Cpu Microarchitecture Jobs

Job ID 2025-14005 Date posted 11/04/2025 Location Bengaluru, India Category Architecture Job Overview The Architecture and Technology Group (ATG) at ARM develops technologies and products for ARMs future architecture roadmap. As part of the evolution of new architecture specifications, modeling and performance analysis is an integral and essential element that enables evaluation of the key architecture features in terms of performance and functionality. This team works alongside the leading architects in their field to develop new models and design performance studies to evaluate and craft new architecture features. Ensuring generational performance gains requires the understanding of not only the core, microarchitecture, and system-level details but also what runs on them. We are seeking a highly motivated and skilled engineer to help enable and drive analysis, characterization and gain deep understanding of sophisticated workloads. This role requires the individual to work with engineers across the globe ranging from hardware architects to software and toolchain experts. This is a highly versatile and visible role that would help shape the next generation CPU microarchitecture through workload performance analysis. Do you want to shape the future of the Arm compute technologies that will enable the next revolution in computing We have an excellent opportunity for a motivated individual to work on crafting our next-generation Arm technologies in the ATG group. Responsibilities Work on analysis of CPU & System benchmarks, dealing with SPEC CPU, Android benchmarks, Browser workloads, AI/ML workloads and other relevant high-performance applications contributing towards performance analysis of cutting edge and future ARM ISA Develop performance models to evaluate new architectural features. Perform detailed workload characterization to study application characteristics, performance bottlenecks and propose architectural solutions, using ARM internal and open-source profiling tools. Collaborate with ARM architects who define future ISA, and IP teams, to define the workload characterization & expand scope of applications & workloads Understand workload build & sampling tools to help providing right workload framework for performance analysis like simpoints, compilation options with GCC/LLVM etc. Create profiling and visualization frameworks to analyse with right level of abstraction. Contribute to automation for streamlining production processes Stay up to date on the latest advancements in application development, workload characterization, performance analysis and modelling technologies. Required Skills And Experience 8+ years in the semiconductor industry working on some aspect of CPU architecture performance modelling or analysis or verification. A background in Electrical Engineering, Computer Engineering, or Computer Science with a good foundation in computer architecture, and microarchitecture. Understanding of general-purpose CPU architecture, CPU microarchitecture, including knowledge of areas such as processor pipelines, caches, and memory hierarchy. Proficient in C/C++ for programming for large-scale software development, familiarity with and Python scripting language skills. Excellent communication, and interpersonal skills with ability to convey effectively complicated solutions. Nice To Have Skills And Experience Experience with CPU performance modelling or performance analysis is plus Understanding of workloads used for performance optimization is a plus Understanding and experience of working with CPU performance modelling methodologies Ability to work in a fast-paced environment with changing priorities and requirements Experience with Unix, scripting, and source control systems (e.g., Git, Subversion). In Return We promise you endless opportunities to experiment and go even further in hardware! From architecture definition to sophisticated core implementation to full custom physical IPs, here you&aposll have our backing to push limits in vital areas. Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email Hybrid Working at Arm Arms approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the teams needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and dont discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Show more Show less

As a CPU Performance Engineer at AMD, you will be a part of the Client CPU Performance Team in Hyderabad, India. Your primary responsibility will be to analyze performance and drive next-generation CPU core hardware and software optimizations for AMD's notebook and desktop processors. This role involves working on key applications, analyzing and tracing system-level workloads, and conducting performance analysis on internal and competitive hardware platforms. Additionally, you will be involved in the development of tools and methodologies for workload analysis and data collection. To excel in this role, you should have a strong passion for leading-edge CPU/SoC architecture, design, and verification. Collaboration is a key aspect of this position, as you will work closely with architects and engineers from different locations and time zones. Your analytical and problem-solving skills will be put to the test as you identify areas for improvement in AMD products, run performance simulations, and debug performance issues. Your responsibilities will also include interacting with various teams such as microprocessor architects, software optimizers, compiler teams, and verification engineers to address architectural performance issues. The ideal candidate should have 3-15 years of prior industry/academic experience and possess a strong background in computing software, computer architecture, system simulation, and performance evaluation. Proficiency in mathematical and statistical modeling, experience with x86 instruction set processors, and expertise in C/C++ programming and software engineering concepts are essential for this role. A degree in Electronics/Computer Engineering or Computer Science with an emphasis on computer architecture is preferred. At AMD, we are committed to pushing the boundaries of innovation to solve the world's most critical challenges. If you are someone who thrives in a collaborative environment, has a passion for cutting-edge technology, and is eager to contribute to the advancement of CPU performance optimization, we invite you to join our team and be a part of transforming lives with AMD technology.,

THE ROLE: We are looking for a results-driven and strategic Director of x86 CPU Performance Verification to lead the development, implementation, and scaling of our performance verification strategy across next-gen CPU cores. In this critical leadership role, you will be responsible for managing a world-class team, defining infrastructure and methodology, and ensuring our CPUs meet and exceed their performance targets from early RTL through post-silicon. You ll work across architecture, design, functional verification, and software teams to bridge performance intent with silicon reality. If you thrive in fast-paced environments, love solving performance bottlenecks, and are passionate about building and mentoring high-impact teams this is the opportunity for you. We are seeking a visionary and technically accomplished Director of CPU Cores Performance Verification to lead our efforts in verifying and optimizing performance for next generation x86 CPU cores. The ideal candidate will have deep expertise in CPU microarchitecture, performance modeling, and verification, with a strong background in performance infrastructure, emulation, and AI-driven methodologies. THE PERSON: You are a visionary leader with deep technical expertise in CPU microarchitecture and performance validation. You combine strong engineering fundamentals with the ability to scale teams and systems. You are comfortable navigating ambiguity, influencing stakeholders across domains, and delivering results under pressure. You lead with empathy, invest in people, and believe that high-performing teams are built on trust, feedback, and a shared sense of purpose. KEY RESPONSIBILITIES: Team Leadership Lead and mentor a high-performing team of performance verification engineers. Foster a culture of innovation, technical rigor, and continuous improvement. Provide strategic direction across multiple concurrent verification programs. Program Leadership Define and execute the performance verification strategy for high-performance x86 CPU cores. Collaborate with architecture, u-arch, RTL, performance modeling, firmware, and software teams to define and validate performance KPIs. Ensure timely delivery of simulation/emulation results, and optimization feedback loops. Performance Analysis & Correlation Develop and execute performance verification plans targeting IPC, latency, throughput, and power efficiency. Validate and debug Performance Monitoring Counters (PMC) to ensure accurate performance visibility. Drive correlation between RTL and performance models, ensuring architectural intent is met. Analyze performance bottlenecks using simulation, emulation, and silicon data. Toolchain & Methodology Build and maintain scalable, modular performance verification infrastructure. Lead emulation-based performance setup and debug, enabling early performance validation. Integrate performance regression, profiling, and analysis flows using industry-standard and custom tools. Collaborate with compiler and OS teams to ensure software stack alignment with hardware performance goals. AI-Driven Infrastructure Drive the development of AI/ML-based infrastructure to automate performance analysis, anomaly detection, and efficiency improvements. Leverage data-driven techniques to optimize verification coverage and reduce debug cycles. Cross-Functional Collaboration Partner with x86 architecture, RTL design, physical design, and software teams to ensure performance targets are met. Influence design decisions through data-backed performance insights. Stakeholder Management Align verification goals with business and product roadmaps. Communicate performance status, risks, and trade-offs to executive leadership and stakeholders. Industry Awareness Stay current with trends in CPU architecture, performance modeling, and verification technologies. Evaluate and adopt emerging tools and techniques to maintain a competitive edge. PREFERRED EXPERIENCE: 20+ years of industry experience with performance modeling and simulation tools (e.g., cycle-accurate simulators, emulators) with strong background in CPU microarchitecture, performance analysis, and system-level performance verification. Proven leadership in managing large, cross-functional engineering teams. Familiarity with PMC DV, latency and throughput validation, emulation platforms, and performance debug flows. Deep understanding of x86 ISA, microarchitecture, and performance metrics. Experience in developing performance test suites, performance triage tools, and simulation/emulation infrastructure. Expertise in performance analysis tools, correlation techniques, and workload optimization. Strong analytical and problem-solving skills with a data-driven mindset. Excellent communication and interpersonal skills. Deep knowledge of modern out-of-order CPU cores, memory subsystems, and performance modeling is a plus. Experience with ML/AI techniques/frameworks for performance triage, infrastructure automation and prediction is a plus. Exposure to high-performance computing (HPC), virtualization, or server-class CPUs. Background in hardware/software co-design and performance-aware compiler optimizations. Familiarity with pre-silicon and post-silicon debug methodologies. ACADEMIC CREDENTIALS: Bachelors/Masters/Ph.D in electrical engineering, Computer Engineering, or related field.

Qualcomm India Private Limited is a leading technology innovator that strives to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. This involves working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and develop innovative solutions. To qualify for this position, you should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field along with 4+ years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years or a PhD with 2+ years of relevant work experience would be considered. We are seeking bright ASIC design engineers with strong analytical and technical skills to be part of a dynamic team responsible for delivering Snapdragon CPU design for Mobile, Compute, and IOT markets. Key responsibilities include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be involved in creating design experiments, conducting PPA comparison analysis, and collaborating closely with RTL design, Synthesis, low power, Thermal, Power analysis, and Power estimation teams to optimize Performance, Power, and Area (PPA). Additionally, developing Place & Route recipes for optimal PPA, tabulating metrics results for analysis, and contributing to the ASIC flow with low power, performance, and area optimization techniques are crucial aspects of this role. The ideal candidate should have 10-15 years of High-Performance core Place & Route and ASIC design Implementation work experience. Proficiency in Place & Route with FC or Innovus, experience with STA using Primetime and/or Tempus, and strong problem-solving skills are preferred qualifications. Knowledge in constraint generation and validation, power domain implementation, formal verification, scripting languages like Perl/Tcl, Python, C++, as well as exposure to Verilog coding and CPU micro-architecture will be advantageous. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. The company's work environment is inclusive and supportive of individuals with disabilities. Applicants should adhere to all relevant policies and procedures, including security measures and confidentiality of company information. Qualcomm does not accept unsolicited resumes or applications from staffing agencies. For more information about this role, please reach out to Qualcomm Careers.,

Qualcomm India Private Limited is a leading technology innovator that aims to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, test systems, FPGA, and/or DSP systems to launch cutting-edge products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. To be considered for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field along with 4+ years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years of experience or a PhD with 2+ years of experience is also acceptable. The ideal candidate should possess strong analytical and technical skills, especially in ASIC design. Responsibilities for this position include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be expected to create design experiments, conduct detailed PPA comparison analysis, collaborate with various teams for optimization, and develop Place & Route recipes for optimal PPA results. Qualifications required for this role include 6-15 years of experience in High-Performance core Place & Route and ASIC design Implementation. Preferred qualifications involve extensive experience in Place & Route with FC or Innovus, knowledge of complete ASIC flow with optimization techniques, proficiency in STA using Primetime and/or Tempus, and skills in Perl/Tcl, Python, C++, among others. Problem-solving abilities, experience with CPU micro-architecture, low power implementation techniques, and clock tree implementation techniques are also desired. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If accommodation is needed during the application/hiring process, individuals can contact Qualcomm for support. The company expects its employees to adhere to all applicable policies and procedures, including confidentiality requirements. Staffing and recruiting agencies are advised that only individuals seeking a job at Qualcomm should use the Careers Site. Unsolicited submissions from agencies will not be accepted. For more information about this role, interested individuals can contact Qualcomm Careers directly.,

Ventana Micro Systems is at the forefront of the two hottest trends that are revolutionizing the semiconductor industry: RISC-V and Chiplet Architecture. Check out our CEO talking with global tech analyst Patrick Moorhead about how Ventana combines the extensibility of RISC-V with chiplet technology to create customer-driven innovation for best-in-class solutions for the data center. Ventana is well-funded and backed by some of the largest strategic investors in the industry with the goal of building best-in-class CPU cores for cloud, enterprise, 5G, and Edge computing. We invite you to join the revolution and contribute to one of the Hottest Semiconductor startups in the industry. CPU Micro Architect /Logic Designer Responsibilities: Develop and refine microarchitecture, write design specifications, and deliver and maintain RTL for CPU Core and/or system-level sub-units Work with physical design engineers to physically realize Core/subsystem RTL using deep sub-micron process technologies Work with design verification/validation engineers to effectively test and debug Core/subsystem-level RTL in simulation, prototyping platforms, and silicon Help model, analyze, debug, and address performance issues and opportunities Qualifications Required: 8+ years industry experience working on RTL for high performance CPU or GPU, memory subsystem, or related system-level designs Bachelors or Masters degree in related engineering field Ability to work independently and across geographies Strong domain knowledge of computer architecture Skills Desired: Verilog/SystemVerilog development experience Industry experience with CPU microarchitecture (e.g. x86, ARM, SPARC, MIPS, RISC-V, POWER) and/or coherent caching systems Experience with high frequency design considerations (timing, power, multiple clock domains, etc.) Experience with typical front-end tools including: Verilog simulators, waveform viewers, and linting tools, as well as logic synthesis and place and route Experience in compiled and/or interpreted (Python, perl) languages Unit or feature ownership throughout the project lifecycle Post-silicon validation Bachelors or Masters degree in computer science or related engineering fields EEOE COVID-19 Ventana encourages all employees to be fully vaccinated (and boosted, if eligible) against COVID-19. We do require Proof of vaccination (or proof of a negative PCR test) to work in the office or meet with customers/ business partners. NOTICE: External Recruiters/ Staffing Agencies: Ventana Micro instructs agencies not to engage with its employees to present candidates. Employees are not authorized to enter into any agreement regarding the placement of candidates. All unsolicited resumes received as gratuitous submissions. We reserve the right to directly contact any candidate speculatively submitted by a third party. Such contact will not constitute acceptance of any contractual arrangement between Ventana and the agency, and Ventana will not be liable for any fees should it choose to engage the candidates services. All external recruiters and staffing agencies are required to have a valid contract executed by Ventanas CFO. Please Note: Fraudulent job postings/job scams are increasingly common. Our open positions can be found through the careers page on our website.,

Role Overview: Join IBM's world-class hardware engineering team to design and lead the development of high-performance processor front-end pipeline units. This role drives architectural innovation for the systems powering next-gen AI and quantum computing. Key Responsibilities: Lead architecture and RTL design of CPU front-end components: Instruction Cache (I-Cache), Instruction Fetch, Branch Prediction, Instruction Decode Drive high-level design discussions and propose innovative microarchitectural solutions. Estimate effort, area, and wiring requirements for new features. Collaborate across design, verification, DFT, physical design, firmware, and software teams. Ensure design meets functional, area, power, and timing goals. Own and support silicon bring-up and validation in post-silicon labs. Mentor junior engineers and represent logic design in global technical forums. Required Qualifications: Bachelor's in Electrical/Computer Engineering or related field 8+ years experience in microarchitecture and RTL design of CPU front-end units Expertise in branch prediction strategies and high-frequency pipeline designs Proficiency in Verilog or VHDL for RTL development Hands-on experience with silicon bring-up and debug Solid understanding of Out-of-Order, Superscalar, and Multi-threaded architecture Knowledge of modern processor architectures (e.g., x86, ARM, RISC-V) Familiarity with object-oriented or functional programming and scripting languages Preferred: Master's Degree in EE, CE, or CS Prior leadership of a team through a full processor core design cycle