Role Overview: Join IBM's world-class hardware engineering team to design and lead the development of high-performance processor front-end pipeline units. This role drives architectural innovation for the systems powering next-gen AI and quantum computing. Key Responsibilities: Lead architecture and RTL design of CPU front-end components: Instruction Cache (I-Cache), Instruction Fetch, Branch Prediction, Instruction Decode Drive high-level design discussions and propose innovative microarchitectural solutions. Estimate effort, area, and wiring requirements for new features. Collaborate across design, verification, DFT, physical design, firmware, and software teams. Ensure design meets functional, area, power, and timing goals. Own and support silicon bring-up and validation in post-silicon labs. Mentor junior engineers and represent logic design in global technical forums. Required Qualifications: Bachelor's in Electrical/Computer Engineering or related field 8+ years experience in microarchitecture and RTL design of CPU front-end units Expertise in branch prediction strategies and high-frequency pipeline designs Proficiency in Verilog or VHDL for RTL development Hands-on experience with silicon bring-up and debug Solid understanding of Out-of-Order, Superscalar, and Multi-threaded architecture Knowledge of modern processor architectures (e.g., x86, ARM, RISC-V) Familiarity with object-oriented or functional programming and scripting languages Preferred: Master's Degree in EE, CE, or CS Prior leadership of a team through a full processor core design cycle

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Lead Logic Design Engineer