ASIC RTL Design Engineer (NOT FPGA RTL)

5 - 25 years

0 Lacs

Posted:1 day ago| Platform: Linkedin logo

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On-site

Job Type

Full Time

Job Description

Key skills with hand on:

Experience:

Work Location:

Education:


Detailed JD:

IP RTL design targeted for SOC, Static checks, some basic protocols

Expertise in SoC subsystem/IP design

Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog

Lint, CDC

Knowledge of synthesis and low power is a plus

AMBA

Good understanding of timing concepts

Knowledge of one or more of the interface protocols

PCIe/DDR/Ethernet/I2C,UART/SPI

Expertise in setting up and using tools like

  1. Spyglass Lint/CDC

  2. Synopsys DC

  3. Verdi/Xcellium

Understanding of scripting languages like Make flow, Perl ,shell, python etc

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