Posted:1 week ago|
Platform:
On-site
Full Time
Our creative and versatile Physical Design team in Bangalore, India. As a member of this team you will be involved in creating next generation innovative networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance die size optimization.
You are an ASIC engineer with 6+ years of related work experience with a broad mix of technologies including:
You should also have hands on experience with the following Tool sets
Cisco
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