Minimum qualifications:
- Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
- 3 years of experience in DFT design or CAD.
- Experience with DFT EDA tools like Tessent.
- Experience with scripting in languages like Python and Tcl.
- Experience in developing and maintaining DFT flows and methodologies.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.
- Experience in advanced technology nodes.
- Experience with DFT for a medium to complex subsystem with multiple physical partitions.
- Experience with developing software pipelines for managing large-scale engineering data and training models.
About The Job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.In this role, you will focus on automating DFT (Design for Test) workflows, which involves creating frameworks in Python and building workflows for DFT RTL (Register-Transfer Level) and pattern generation, as well as SoC (System-on-Chip) design and validation automation. Your responsibility will be improving execution efficiency.We utilize Agentic AI, which means designing and deploying multi-agent systems to execute complex tasks like silicon design automation and optimization within existing CAD (Computer-Aided Design) environments. This requires the seamless integration of advanced CAD tools with powerful, Python-based AI models to establish a truly collaborative design ecosystem.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.
Responsibilities
- Anticipate and address application-specific integrated circuit (ASIC) design issues, analyze, and validate design by leveraging test results, and suggest or implement design improvement and determine ASIC design methodologies and own cross-functional SOC development activities.
- Develop and support various electronic design automation (EDA) tool infrastructure and flows.
- Collaborate with cross-functional teams to debug failures (e.g., boards, software, manufacturing, design, thermal issues, etc.).
- Optimize cost and efficiency while delivering predictable and reliable license or compute resources, including runtime and optimal use of storage.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
