3.0 - 5.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Minimum qualifications: Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. 3 years of experience in DFT design or CAD. Experience with DFT EDA tools like Tessent. Experience with scripting in languages like Python and Tcl. Experience in developing and maintaining DFT flows and methodologies. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field. Experience in advanced technology nodes. Experience with DFT for a medium to complex subsystem with multiple physical partitions. Experience with developing software pipelines for managing large-scale engineering data and...

Posted 17 hours ago

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Principal Engineer Infineon Technologies

0.0 years

0 Lacs

ahmedabad, gujarat, india

On-site

Strong experience in Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs Job Description In your new role you will: Implement high-performance, low-power, and area-efficient digital designs. Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis. Optimize designs for power, performance, and area, and meet PPA goals. Power analysis using PT-PX or equivalent flow. Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs. Define and evaluate constraints and signoff Test/DFT mode timing requirement Your Profile You are best equipped for this task if you have: Strong fundamentals and experi...

Posted 2 months ago

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DFT - MBSIT AND ATPG Modernize Chip Solutions (MCS)

4.0 - 8.0 years

0 Lacs

karnataka

On-site

You should have a minimum of 4 years of experience in the field. You must be proficient in using Synthesis and netlist validation tools, particularly LEC and Spyglass checks, as well as scan insertion and DRC debug. It is essential to be well-versed in both Synopsys and Mentor Graphics DFT flows. Your expertise should also include experience in Scan Compression for Hierarchical and Modular EDT, ATPG, and Coverage debug, along with the ability to manage multiple clock domains and familiarity with the OCC flow. You should have practical experience in BIST and BISR insertion and Validation with SMS and MBIST Architect. Hands-on experience with JTAG, IJTAG, and SSN is required. You should be fam...

Posted 3 months ago

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