As a member of the G&E SoC DFT Team, the successful candidate will own the DFT responsibilities for the next gen of AMD SoCs. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: The candidate must have thorough knowledge of DFT basics such as scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory. Need to work with product engineering team for Silicon Bring-up and also support post-silicon debug. Interfacing with the design teams to ensure DFT design rules and guidelines are met Interact with PD and Front End Integration team for Scan Insertion Generating high quality manufacturing test patterns for stuck-at, transition fault models and CA model Simulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Developing, enhancing and maintaining scripts as necessary Able to technically guide and mentor junior folks in the team PREFERRED EXPERIENCE: Experience in creating and implementing complex chip-level DFT architecture Experience in DFT implementation including Scan insertion, ATPG and Simulations Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression Experience in debugging low coverage and DRC fixes Proficient in logic design using Verilog Experience of debugging test pattern issues Support the Silicon bringup activities to guarantee highest stability of the test pattern Knowledge of MBIST is a plus. Knowledge of synthesis is a plus Experience with post-silicon debug Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc Any Tessent Scan/ATPG certifications is a plus Excellent presentation and inter-communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Prior experience as DFT engineer

We are looking for a talented Member of Technical Staff (MTS) with expertise in SoC Scan, Automatic Test Pattern Generation (ATPG), pattern retargeting, and simulations. The ideal candidate will play a crucial role in developing and verifying robust DFT solutions to ensure the quality and testability of our cutting-edge SoC designs. Key Responsibilities: Develop and execute SoC Scan insertion strategies and ensure integration across various modules. Generate and validate ATPG patterns to achieve high fault coverage for SoC designs. Perform pattern retargeting and conduct thorough simulations to ensure test reliability and efficiency. Debug and resolve test coverage gaps or failures during pattern simulations and silicon testing. Collaborate with cross-functional teams to ensure seamless DFT implementation and validation processes. Optimize test methodologies to improve yield and reduce test time. Required Skills: Strong hands-on experience in SoC Scan implementation and ATPG pattern generation. Proficiency in pattern retargeting and running simulations to ensure high-quality results. Familiarity with industry-standard DFT tools like Mentor Tessent, Synopsys TetraMAX, or Cadence Modus. Solid understanding of RTL design, verification, and debugging. Expertise in scripting languages (e.g., Python, TCL, Perl) for test process automation. Problem-solving skills for silicon debug and test failure analysis. Preferred Qualifications: Experience with low-power ATPG techniques and fault diagnostics. Knowledge of advanced DFT features such as compression and hierarchical ATPG. Exposure to post-silicon validation and production test flows. Education: Bachelors/Masters degree in Electrical/Electronics Engineering, Computer Engineering, or related field.

Job Title: Member of Technical Staff (MTS) DFT Verification Experience: 6+ years Location: Bangalore Job Description: We are seeking a dedicated and experienced Member of Technical Staff (MTS) specializing in DFT Insertion and Verification . The candidate will play a key role in ensuring the robustness and reliability of Tile and SoC designs by implementing and verifying advanced test architectures. Key Responsibilities: Perform SMS (Structural Mode Scan) Insertion and verification at both Tile and SoC levels. Design and verify Memory BIST (Built-In Self-Test) architectures, including initialization and integration. Implement and validate memory repair strategies, including fuse programming (eFuse) and redundancy management. Debug and optimize DFT flows to meet high fault coverage and manufacturability standards. Collaborate with cross-functional teams to ensure seamless DFT integration across various design phases. Analyze test results, resolve silicon and test-related issues, and contribute to yield improvements. Required Skills: Expertise in SMS Insertion and verification for Tile and SoC level designs. Proficiency in Memory BIST architecture, including repair mechanisms and eFuse configuration. Hands-on experience with DFT tools like Mentor Tessent, Synopsys DFT Compiler, or Cadence Modus. Strong scripting skills in Python, Perl, or TCL for automation of test flows. Knowledge of RTL design and debugging (Verilog/VHDL). Excellent problem-solving and analytical skills, especially in debugging silicon failures. Preferred Qualifications: Experience with low-power DFT methodologies and advanced compression techniques. Familiarity with industry standards for JTAG and boundary scan. Hands-on experience with post-silicon validation, bring-up, and characterization.

We are seeking an experienced HPC Systems Engineer with 7+ years of expertise in high-performance computing (HPC) environments. This role requires hands-on experience with Python, Kubernetes (K8s), Slurm, OpenStack, and Ansible , along with the ability to support external clients in live troubleshooting sessions. The PERSON: The ideal candidate will have deep technical knowledge of drivers, troubleshooting methods, and system-level debugging and will play a key role in managing, optimizing, and troubleshooting HPC clusters and cloud-based HPC environments. KEY RESPONSIBILITIES: HPC System Administration & Troubleshooting Manage and optimize HPC clusters, ensuring high availability and performance. Troubleshoot GPU, CPU, network drivers, firmware, and OS-level issues. Debug storage, networking, and job scheduling bottlenecks in Slurm-based environments. Kubernetes & Cloud HPC Environments Deploy and manage HPC workloads in Kubernetes for AI/ML and parallel computing. Optimize OpenStack-based HPC clusters with Ceph, Cinder, and Neutron for cloud scalability. Implement containerized HPC workflows using Kubernetes and OpenShift. Automation & Infrastructure as Code (IaC) Develop Ansible and Terraform scripts for provisioning and managing HPC resources. Automate job scheduling, cluster monitoring, and log analysis using Python. Optimize CI/CD pipelines for HPC and AI/ML applications. Performance Tuning & Benchmarking Benchmark and optimize multi-node HPC workloads (MPI, NCCL, ROCm, CUDA). Tune OS parameters, networking (InfiniBand, RoCE), and Slurm configurations for peak performance. Enhance HPC storage performance (Ceph, Lustre, NFS) and distributed computing efficiency. Client Support & Collaboration Provide real-time technical support and troubleshooting for HPC users. Engage with developers, DevOps, and system administrators to optimize cluster performance. Document solutions, best practices, and contribute to internal knowledge bases. PREFERRED QUALIFICATIONS: Experience with AMD MI300, MI2X0 GPUs, ROCm, MPI, UCX, or XPMEM. Exposure to containerized workloads using Singularity or Docker in HPC. Familiarity with OpenStack deployment automation (e.g., TripleO, Kolla, or OpenStack-Ansible). Experience in customer-facing technical roles, with a strong ability to troubleshoot live issues.

We are seeking an experienced RTL Design Leader/Manager with strong technical and leadership skills, who thrives in a fast-paced environment, to lead a talented team of engineers. It is a challenging position that involves working at a fast pace & agility to meet Quality & schedule for the IP delivery. Come join the AMD team! THE ROLE: We are looking for a Senior Manager Silicon Design Engineering to lead a team of talented engineers in developing NPU IP. This IP goes to several products including client and embedded products and serves as AI inference accelerator. This role requires deep understanding of design implementation and flows, tools and methodologies. THE PERSON : The ideal candidate should have demonstrated experience in leading front-end design and integration of sub-systems for complex SOCs. The candidate must be able to communicate effectively and work optimally with different teams across AMD. The candidate must have excellent analytical and problem-solving skills. KEY RESPONISIBILITES : Manage design and front-end integration team for NPU. Drive the design execution using technical expertise, mentoring team of engineers & being responsible for overall execution Quality & schedule. Define and implement RTL design methodologies and best practices. Lead team, meet schedule commitments and provide strong support to various customers. Ensure Design meets performance, power and Area targets & verification coverage for successful silicon. Work with verification and physical design teams to achieve high quality design and successful tape out Collaborate with cross-functional team for successful and on-time delivery of NPU. PREFERRED EXPERIENCES : Strong design experience in ASIC designs, RTL design in Verilog/System Verilog, preferably in complex SOC like CPU/GPU. Modern SOC tools such as Spyglass, Questa CDC, Cadence Conformal Low Power, VCS simulation Experience for power domains and power islands using UPF flows and Cadence Conformal Low Power. Expertise in circuit timing/STA, and practical experience with Prime Time or equivalent tools Hands-on with TCL, Perl, Python scripting, Strong verbal and written communication skills

Lead and develop timing methodologies, establish SDC constraints, and automate processes for special timing checks, ensuring design convergence and managing ECOs effectively. Perform static timing analysis setup and sign-off for multi-corner, multi-voltage processes to align with PPA targets, initially at the hierarchical level and subsequently at the top-level, reviewing the timing arcs for the .lib generation. Collaborate closely with RTL, DFT, and IP teams to ensure smooth integration and address physical design concerns affecting scan shift and scan capture modes for DFT. Identify opportunities to optimize clock skew and insertion delay across various corners and modes. Evaluate the clock/reset-domain-crossing (CDC/RDC) issues at the netlisting stage and offer feedback on design fixes or establish waivers if the changes are not feasible. Implement power-saving strategies, such as power gating, multi-voltage domains, and clock gating, to meet low-power objectives while preserving performance standards. Create and refine custom scripts using Tcl, Perl, or Python to enhance workflow efficiency and streamline physical design operations. Mentor and support junior physical design engineers, disseminating best practices and providing technical guidance to elevate team proficiency and performance. PREFERRED EXPERIENCE: Over 8-10+ years of professional experience in constraints generation, synthesis, static timing analysis (STA), and IP-level timing and physical design, with a preference for high-performance SerDes designs. Proven ability in timing analysis, convergence, timing ECOs, and .lib generation. Experience with STA closure on PHYs & understanding the timing requirements across digital and analog macro interfaces is a plus. Proficient in physical design tools such as Synopsys ICC2, Primetime, and the ASIC design flow. Skilled in scripting with Tcl, Python, or Perl to automate and streamline physical design tasks. Excellent problem-solving, leadership, and communication skills and values team culture. Capable of thriving in fast-paced environments and managing multiple projects simultaneously.

Your curiosity will drive your learning and innovation to improve how we as a group, and an organization, can get better every day. Your peers will provide you a results-oriented and encouraging environment for your career growth, fueling your opportunity to be a part of Delighting Our Customers. KEY RESPONSIBILITIES: Problem solving across multiple software layers, (user space, kernel, applications, libraries) and hardware. Optimization/development of the CPU performance stack (applications, libraries) for AMD server processors. Analyze and solve performance, scalability bottlenecks when code is running on multi-core, multi-node deployments. Innovate and publish papers, patents and participate in technical conferences to advance AMD technologies. Continuously learn and grow along with evolving X86 server CPU architecture and application landscape. Lead collaborative approaches with multiple teams. Mentor others to achieve integrated projects Must be a self-starter, and able to independently drive tasks to completion PREFERRED EXPERIENCE: Very strong data structure and algorithmic skills. Experience in identifying performance bottlenecks, and designing/implementing optimizations to relieve analyzed bottlenecks. Experience in software development using C/C++ and debugging skills on multicore systems. Experience in performance analysis for data center, HPC (High Performance Computing), MPI (Message passing Interface) applications. Experience in x86 (or other architecture based) optimizations. Understanding of Cache sub-system, Instruction Set Architecture, pipeline (for any CPU). Bonus skills: Experience on Intel MKL libraries, Linear Algebra, FFT, x86 assembly programming. Knowledge of one or more CPU Profiling tools ACADEMIC CREDENTIALS: Bachelor s or Masters degree in Computer or Electrical Engineering or equivalent

We are looking for a highly talented and passionate Software Development Manager to lead a team of Smart engineers developing SW drivers and solutions for next generation AMD platforms. He shall have strong motivation and interest to learn new technology, process and be versatile to expand to various domains. Strong x86 architecture background and/or Platform architecture background is a plus. Should have BE/MTECH/MS degree in Electronics, Computer Science, or related engineering field from reputed university. Should have 15+ yrs. of SW development experience with 10+ years in technical leadership and 5+ years in building and managing high performing software engineering team. Should have strong technical knowledge of semiconductor industry, lead teams as a technical influencer and deliver exceptional results. Key responsibilities As the Manager of the India team, the individual will be responsible for leading a high-caliber team of experienced SW engineers who are responsible for development and delivery of platform SW solutions for AMD s Next Gen products. Define and manage team deliverables. Project and plan for resources based on future needs Coordinate dependencies with other stakeholders (Design architects, Validation and Customer engineer teams) Collaborate with multi-functional teams contributing to program execution. Coach and mentor career growth for each individual team members so that they can bring out the best potential. Required Skills Experience in System level and/or large-scale software development Knowledge of variety of programming languages, codes, and processes. Expert in troubleshooting and ability to assess quickly complex system software solutions Understanding of CPU and / or system architecture with awareness of platform SW stack components (System BIOS, Device drivers, I/O, tools, etc.) Excellent interpersonal, written, and verbal communication skills. Manage project resource, cost, and timelines. Raise team productivity and effectiveness by defining and driving metric-driven software engineering best practices. Knowledge of Pre-silicon and Post-silicon product life cycle will be added advantage. Understanding and hands-on experience with Linux kernel driver development. Knowledge of Linux kernel upstream process is an added advantage. Preferred leadership experience: Should have managed a team of at least 10 engineers with complex projects. Demonstrated experience in team building, organization, budget planning, project management, and dependency tracking. Should have passion for code quality, operational excellence, and people development. Excellent communication skills, proactiveness and ability to work with minimal input and directions. Build an effective development organization by driving hiring of senior level engineers, developing, and managing the group and conducting performance reviews of team members. Academic Credentials: Bachelors/Master s in Engineering. Experience: 12 15 years.

The primary responsibility is the validation of BootROM, which includes the following tasks: Develop and execute test cases to validate all boot peripherals from where the FSBL (First Stage Boot Loader) is copied. Example: xSPI, SD, eMMC, UFS, USB Create and execute test cases to validate all proprietary boot sequences. Develop and execute test cases to validate all internal boot modes. Write and run test cases to validate all supported authentication algorithms. Develop and execute test cases to validate all supported encryption/decryption algorithms. Automate tests using Python. Perform testing on prototyping/emulation platforms, including X86 emulation. Identify, document, and track issues using JIRA. Report coverage metrics using tools such as Verdi and add tests to ensure maximum source line coverage. Review requirements and create associated test cases to ensure traceability. Collaborate with different teams to resolve any blockers. Engage in constructive discussions with the design team to improve the quality of the BootROM. Conduct security threat analysis using internal tools. Adhere to safety processes while performing the above tasks.

Responsible for AMD employees payroll and ensure Service Level Agreement (SLA) for timeliness and accuracy of payroll processing and deliverables are achieved. Timely processing of payroll and perform analysis to ensure all relevant data and reports are correct. Working closely with Payroll service provider to ensure accurate and timely payout to our employees Ensuring Payroll service provider have all information at hand to deliver their services Ensure all payroll journal entries on payments, accruals and reversal are correctly posted and reconciled. Perform yearly tax filling of employee s income statement to tax authority Archiving all supporting documents as per retention policy and ensure compliance to all audit requirements. Involve and support in yearly audit activities Perform testing and verification on changes in SAP system (SuccessFactors) Partnering with internal organizations such as Human Resource, Finance, Tax, Accounting, Legal to have the right process in place Analyze existing payroll processes, challenge the status quo, and drive continuous process improvements to enhance efficiency and deliver service excellence to customers. Serve as the subject matter expert for payroll processes across multiple countries, representing the region during assigned projects and/or system implementations. Handle ongoing employee helpdesk inquiries related to payroll, providing clear and effective communication to explain pay, deductions, benefits, and other payroll-related issues Responsible for multitasking and coordinating assigned tasks across multiple countries. To support statutory compliance, internal/external audits, benefits administration, and payroll system/process changes Qualification Requirements (Skills Knowledge): Degree in accounting or equivalent accounting processional qualification Knowledge on SAP and Microsoft Office application software are essential Proven experience in payroll or a related field, with a strong understanding of payroll processes. Excellent communication and interpersonal skills to interact effectively with employees. Understanding of relevant payroll laws and regulations At least 4-5 years working experience in the same role and handling multi-national company Possess good analytical and problem-solving skills

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop/Maintain tests for functional verification and performance verification at the core level Build testbench components to support the next generation IP Maintain or improve current test libraries to support IP level testing Create hardware emulation build to verify the IP functional performance Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility Provide technical support to other teams PREFERRED EXPERIENCE: Good at C/C++ Familiarity with SystemVerilog and modern verification libraries like UVM Experience/Background on Computing/Graphics is a benefit Experience with OpenGL/OpenCL/D3D programming is a benefit ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

The ideal candidate should be passionate about software development and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. KEY RESPONSIBILITIES: Software Development Develop, and maintain software applications and systems. Write clean, efficient, and well-documented code. Debug and resolve software defects and issues. Apply design patterns to sole architectural problems. Collaboration Work with cross-functional teams, including developers, product managers, to deliver high-quality software solutions. Host meetings to discuss status of ongoing tasks with the team. Work with Quality Assurance Team on problem resolutions. Testing and Quality Assurance : Identify and fix bugs, performance issues, and other problems. Develop personal tests to ensure software reliability. Documentation : Create and maintain technical documentation and design specifications. Continuous Improvement : Stay up-to-date with emerging technologies, tools, and best practices in software development. Propose and implement improvements to existing systems and processes. PREFERRED EXPERIENCE: Proficiency in one or more programming languages (C++, C#, Python, etc.). Experience with software development frameworks and tools (QT, .NET, MS WDK, React, Angular, Windows Installer, INF etc). Knowledge of version control systems (Git, Perforce). Understanding of software development methodologies (Agile). Experienced in Windows Platforms (Windows 10, 11, WorkStation). Experience with machine learning or AI technologies is a plus. Familiar with CI/CD pipelines Dev Ops and automatic deployment strategies. Experience in code signing, licensing, and software update mechanisms. Effective communication and problem-solving skills Strong leadership skills, able to lead the team to resolve various problems and develop new features Attention to detail and a commitment to delivering high-quality work ACADEMIC CREDENTIALS: Bachelor s or Masters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

As a senior member of the SerDes IP Physical Design (PD) team, your primary responsibility will be overseeing the timing and implementation of crucial PHY IPs. You will focus mainly on the Design-For-Test (DFT) logic and its integration with operational mode logic. A strong grasp of DFT concepts is advantageous, as it provides a comprehensive perspective to achieve design specifications. This role demands profound technical expertise in physical design tools and methodologies, along with the capability to lead and mentor a group of physical design engineers in future. KEY RESPONSIBILITIES: Lead and develop timing methodologies, establish SDC constraints, and automate processes for special timing checks, ensuring design convergence and managing ECOs effectively. Perform static timing analysis setup and sign-off for multi-corner, multi-voltage processes to align with PPA targets, initially at the hierarchical level and subsequently at the top-level, reviewing the timing arcs for the .lib generation. Collaborate closely with RTL, DFT, and IP teams to ensure smooth integration and address physical design concerns affecting scan shift and scan capture modes for DFT. Identify opportunities to optimize clock skew and insertion delay across various corners and modes. Evaluate the clock/reset-domain-crossing (CDC/RDC) issues at the netlisting stage and offer feedback on design fixes or establish waivers if the changes are not feasible. Implement power-saving strategies, such as power gating, multi-voltage domains, and clock gating, to meet low-power objectives while preserving performance standards. Create and refine custom scripts using Tcl, Perl, or Python to enhance workflow efficiency and streamline physical design operations. Mentor and support junior physical design engineers, disseminating best practices and providing technical guidance to elevate team proficiency and performance. PREFERRED EXPERIENCE: Over 8-10+ years of professional experience in constraints generation, synthesis, static timing analysis (STA), and IP-level timing and physical design, with a preference for high-performance SerDes designs. Proven ability in timing analysis, convergence, timing ECOs, and .lib generation. Experience with STA closure on PHYs & understanding the timing requirements across digital and analog macro interfaces is a plus. Proficient in physical design tools such as Synopsys ICC2, Primetime, and the ASIC design flow. Skilled in scripting with Tcl, Python, or Perl to automate and streamline physical design tasks. Excellent problem-solving, leadership, and communication skills and values team culture. Capable of thriving in fast-paced environments and managing multiple projects simultaneously.

Responsible for building infrastructure for performance verification and verify performance of X86 processor. Writing specific targeted tests to measure the performance of the processor Involves having a deep understanding of processor micro-architecture and triaging performance issues in RTL and simulator Skillset Debug triage of failures from simulation and emulation environment for CORE or sub level regressions. Writing automatized triages in Perl/Ruby and creating tools using perl/ruby or AMD verification methodology (primarily in C++) to enhance the functional debug and triage process. On a need basis, work on Post-Si bug recreation PREFERRED EXPERIENCE: Experience: 3-15 years experience in processor/ASIC performance correlation. Experience in micro-architecture testing for modern high-performance processors. Experience in writing tests and building infrastructure that tests performance of modern processors. Experience in application performance analysis Programming/Scripting Skills C, C++, Perl, Python. Solid background and understanding of Digital Design, RTL design , improving model performance and Processor Architecture Strong troubleshooting, analytical and debug skills. Prior experience in performance correlation of Processor subsystems is a plus. Excellent knowledge of computer architecture with relevant research and project work or industry experience Strong programming skills (C/C++ and assembly) Basic knowledge of Verilog ACADEMIC CREDENTIALS: Bachelors/Masters in Computer Science/Electrical/Electronics Engineering with relevant course and research work

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environment s Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment . Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience . Scripting language experience: Perl, Ruby, Makefile , shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions . ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Architectural Design : Own architectural design and development of GPU software components, ensuring alignment with industry standards and best practices. Technical Leadership : Act as one of the subject matter experts in GPU technologies, providing guidance and mentorship to junior engineers in the team on complex technical challenges. Work with PMTS and develop strong technical capabilities in the Team Software Development : Design, write, and deliver high-quality open software solutions that enhance GPU performance and capabilities. This includes developing drivers, APIs, and other critical software components. Research and Innovation : Conduct research to explore new technologies and methodologies that can improve GPU performance and efficiency. Propose innovative solutions to meet evolving market demands. Collaboration : Work collaboratively with cross-functional teams, including hardware engineers, system architects, and product managers, to ensure successful integration of GPU technologies into broader systems. Documentation and Standards : Develop comprehensive technical documentation and establish coding standards to ensure maintainability and scalability of software products. THE PERSON: We are looking for a highly motivated and skilled Software Engineer to join our team. You will work with a team of Software Engineers to enable models, libraries, and applications for Instinct GPUs in both on-prem and Cloud environments. Candidates should also have experience analyzing and optimizing the performance of software. Must be self-motivated and possess the ability to work well within a team environment. Minimum 12 years of experience required. QUALIFICATIONS: BE / B-Tech with several years of related experience or M-Tech with years of related experience or PhD with years of related experience in Computer Science or Computer Engineering or related equivalent. Overall 12 years of experience EXPERIENCE - Must have : Strong C++ programming skills Good Python programming skills Performance analysis skills for both CPU and GPU Good knowledge of AI/ML Frameworks and Architecture Basic GPU kernel programming knowledge Experience with software engineering methodologies such as Agile, Scrum, Kanban. Experience in all the phases of software development, from requirement gathering, analysis, design, development, testing to final release. Experience providing clear and timely communication related to status and other key aspects of the project to leadership team Experience developing software in an end customer product delivery environment. Experience with open-source software development including collaboration with community maintainers and submitting contributions. Excellent analytical and problem-solving skills. Ability to work independently and as part of a team. Willingness to learn skills, tools, and methods to advance the quality, consistency, and timeliness of AMD software products. EXPERIENCE - Good to have : Experience with GPU kernel programming using CUDA, HIP or OpenCL. Experience in implementing and optimizing parallel methods on GPU accelerators (NCCL/RCCL, OpenMP, MPI) Experience in PyTorch, TensorFlow, JAX Experience with Singularity, Docker, and/or Kubernetes. Preferred Attributes Proven track record of leading complex technical projects from conception through delivery. Excellent problem-solving skills with the ability to work independently as well as collaboratively within a team environment. Strong communication skills to effectively convey complex technical concepts to both technical and non-technical stakeholders

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environment s Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment . Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience . Scripting language experience: Perl, Ruby, Makefile , shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions . ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

AMD is looking for an influential software engineer who is passionate about improving the performance of key applications and benchmarks . You will be a member of a core team of incredibly talented industry specialists and will work with the very latest hardware and software technology. THE PERSON: The ideal candidate should be passionate about software engineering and possess l eadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. KEY RESPONSIBILITIES: Work with AMD s architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develo p new groundbreaking AMD technologies Participating in new ASIC and hardware bring up s Debugging /fix existing issues and r esearch alternative, more efficient ways to accomplish the same work Develop technical relationships with peers and partne rs PREFERRED EXPERIENCE: 10 years of experience in software development in domains of networking, RDMA, or system software 10 years of experience in software development in domains of networking in one of the following areas: Software data plane applications such as VPP/equivalent. P4/u-code based data plane development RDMA transport development Strong object-oriented programming background, C/C++ preferred Ability to write high quality code with a keen attention to detail Experience with modern concurrent programming and threading APIs Experience working in different operating systems or server environments is a plus Experience with software development processes and tools such as debuggers, source code control systems (GitHub) and profilers is a plus Effective communication and problem-solving skills Experience in performance tuning and debugging system level issues Experience in DPU or AI-NIC development is a huge plus ACADEMIC CREDENTIALS: bachelors or M asters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

AMD is looking for an experienced Analog Mixed Signal engineer to take on the technical challenges within the I/O and PHY Technology Group. This group delivers critical Mixed Signal IP such as highly configurable high-speed memory I/Os/PHYs and Chiplet Interconnect IP (eg UCIE) to various Business Units/SoCs within AMD. The ideal candidate will get to work with circuit and FE architects to accurately model the analog digital interface boundary of high speed mixed signal IPs to accomplish timing integrity goals. KEY RESPONSIBILITIES: Analyze timing constraints for complicated static timing analysis (STA) paths including multistage generated clocks, ZCPs in a variety of mixed signal circuits. Use the appropriate margining methodology for data, clock and async timing paths to improve timing robustness and reliability. Identify noise sources in timing models and feedback to CKT and LAY for appropriate design fixes. Adopt leading industry STA and Timing Char tools to drive timing convergence in mixed signal IP development. Use scripting skills to meet efficiency and quality goals across all timing workflows. Derive best design guidelines for optimal signaling performance that result in minimal skews and insertion delays for various types of data interfaces and clock propagation. Prepare, analyze and report on data integrity and consistency within the macro timing model using spice correlation and data analytics. PREFERRED EXPERIENCE: 6+yrs experience in high-speed 10+Gbps serial and/or parallel analog PHY/IO designs. Experience in FinFet advanced CMOS process nodes with a solid understanding of transistor device performance and fundamentals. Timing closure and Timing char using PrimeTime and NanoTime STA tools is a must. Proficiency in using spice based extraction and simulation tools. Very good understanding of SOC and Custom flows including physical design and IR drop. Strong communication skills with ability to comprehend and present technical ideas & reports across different teams and geographies. Strong analytical and problem-solving skills including the ability to root cause and debug in a fast-paced environment. Possess sound fundamentals and knowledge of analog mixed signal circuits timing collaterals and constraints. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

AMD is looking for an experienced Analog Mixed Signal engineer to take on the technical challenges within the I/O and PHY Technology Group. This group delivers critical Mixed Signal IP such as Chiplet Interconnect IP (e.g UCIe), highly configurable high-speed memory, I/Os/PHYs to various Business Units/SoCs within AMD. The ideal candidate will get to work with Circuit and FE Architects on the design and implementation of complex high speed Analog Mixed Signal IPs with significant Digital and Analog content. K EY RESPONSIBLITIES : Architect the analog-digital interface timing boundary for high-speed analog mixed signal IP designs. Design high speed custom digital sub-modules for high-speed DDR PHY classes and die-to-die PHY. Use the performance-power-reliability trade off matrix to achieve IP goals. Define the appropriate margining methodology and scope for data, clock and async timing paths. Identify noise sources in timing models and feedback to CKT and LAY for appropriate design and/or flow fixes. Analyze timing constraints for complicated static timing analysis (STA) paths including multistage generated clocks, ZCPs in a variety of mixed signal circuits. Adopt leading industry STA and Timing Char tools to drive timing convergence in mixed signal IP development. Derive best design guidelines for optimal signaling performance that result in minimal skews and insertion delays in deep-nm tech nodes for various types of data interfaces and clock propagation schemes. Provide technical guidance to junior team members. Use scripting skills to meet efficiency and quality goals across all timing workflows. P REFERRED EXPERIENCE : 12+yrs experience in high-speed 10+Gbps serial and/or parallel analog PHY/IO designs. Experience in FinFet advanced CMOS process nodes with a solid understanding of transistor device performance and fundamentals. Experience with SerDes or DDR PHY digital logic layer implementation is required. Timing closure and Timing char using PrimeTime and NanoTime STA tools is a must. Proficiency in using spice based extraction and simulation tools. Very good understanding of SOC and Custom flows including physical design and IR drop analysis. Experience working with physical design and functional verification teams. Knowledge of System Verilog and verification methodologies such as OVM and UVM is highly valued. Strong communication skills with ability to ability to comprehend and present ideas & reports across different teams and geographies. Strong analytical and problem-solving skills including the ability to root cause and debug in a fast-paced environment. Possess fundamentals and knowledge of analog mixed signal circuits, timing collaterals and constraints. Proficient in AMS design flows, tools and methodologies. Experience in evaluating and adopting new tools and methodologies to improve design processes. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering