5 Verilog Rtl Jobs

Job Description Arms Solutions group DFT team implements DFT for test-chips and hard-macros to prove Arm&aposs soft IP power, performance, area, and functionality within the context of a SoC using the latest DFT techniques and process technologies. We closely collaborate with RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE. Responsibilities Architect, Implement, and validate innovative DFT techniques on test-chips and hard-macros. Insert DFT logic into SoC-style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE-targeted test patterns to be run on silicon. Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on DFT gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation. Required Skills And Experience This role is for a Senior DFT Engineer with 8+ years of proven experience in Design for Test Experience coding in Verilog RTL, and scripting language like TCL, and/or Perl Proficient in Unix/Linux environments Core DFT skills considered crucial for this position should include some of the following: Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debug Experience with Siemens, Cadence, and/or Synopsys DFT and simulation tools Nice To Have Skills and Experience: Familiarity with IEEE 1149, 1500, 1687 Familiarity with Synthesis and Static Timing Analysis Working knowledge of Siemens DFT tools Ability to work both collaboratively on a team and independently. Innovative and a passion for progress Hard-working and excellent time management skills with an ability to multi-task In Return: Opportunity to work with some of the greatest minds in the industry! Competitive compensation and great benefits! Flexible working hours Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [HIDDEN TEXT] . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arms approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the teams needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and dont discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Show more Show less

As a Senior DFT Engineer at Arms Solutions group DFT team in Bengaluru, India, you will play a crucial role in implementing DFT for test-chips and hard-macros to validate Arm's soft IP power, performance, area, and functionality within the context of a SoC. You will collaborate closely with RTL, Verification, Physical Implementation, and Test engineering teams throughout the project lifecycle, from early investigation to tape-out and silicon test/characterization on ATE. Your responsibilities will include architecting, implementing, and validating innovative DFT techniques on test-chips and hard-macros. You will insert DFT logic into SoC-style designs at the RTL and Synthesis gate levels, validate features, and generate ATE-targeted test patterns for silicon testing. Collaboration with front-end design, verification, synthesis, place-and-route, static-timing-analysis, and test/debug teams will be essential for successful project delivery. The ideal candidate for this role is a Senior DFT Engineer with 8+ years of experience in Design for Test, proficient in Verilog RTL coding, scripting languages like TCL and/or Perl, and Unix/Linux environments. Core DFT skills required include Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, and silicon debug. Experience with Siemens, Cadence, and/or Synopsys DFT and simulation tools is desirable. Nice to have skills include familiarity with IEEE standards, Synthesis, Static Timing Analysis, and Siemens DFT tools. The ability to work collaboratively in a team and independently, coupled with innovative thinking and time management skills, will be valued in this role. In return, you will have the opportunity to work with industry experts, competitive compensation, great benefits, and flexible working hours. Arm values building extraordinary teams and is committed to creating an inclusive work environment. Accommodations during the recruitment process can be arranged by contacting accommodations@arm.com. Arm also supports hybrid working arrangements to promote high performance and personal wellbeing. The specifics of hybrid working for each role will be shared upon application, ensuring a balance between flexibility and meeting business needs. Arm is dedicated to equal opportunities and creating a diverse and inclusive workplace. Join Arm's DFT team in Bengaluru and be part of a dynamic environment where innovation and collaboration thrive!,

The Common Hardware Group (CHG) at Cisco is responsible for delivering silicon, optics, and hardware platforms for core Switching, Routing, and Wireless products. As a part of this team, you will contribute to designing networking hardware for Enterprises, Service Providers, the Public Sector, and Non-Profit Organizations globally. Cisco Silicon One is a groundbreaking silicon architecture that allows customers to utilize top-of-the-line silicon in various network environments. Join us in shaping innovative solutions by working on the design, development, and testing of complex ASICs. In this role, you will collaborate with the team on Verilog RTL and scripted flow implementation of Hardware Design-for-Test (DFT) features to support ATE, in-system test, debug, and diagnostics requirements. You will also be involved in Verilog testbench implementation for verification tests and automation scripts to enhance implementation quality and efficiency. **Minimum Qualifications:** - Bachelor's or Master's Degree in Electrical or Computer Engineering with a minimum of 2 years of experience. - Proficiency in DFT, test, and silicon engineering trends. - Familiarity with JTAG protocols, Scan and BIST architectures, ATPG, and EDA tools. - Verification skills in System Verilog Logic Equivalency checking and Test-timing validation. **Preferred Qualifications:** - Understanding of VLSI circuit physical behaviors in silicon. - Knowledge of timing concepts and EDA tools usage. - Strong verbal communication skills and adaptability in a dynamic environment. - Proficiency in scripting/coding languages such as Tcl, Python, Perl, or C/C++. Cisco is committed to embracing diversity, fostering innovation, and driving digital transformation. With a focus on inclusive teamwork and a culture of creativity, we encourage individuality and support continuous learning and growth. At Cisco, we value accountability, boldness, and diversity of thought. Join us in our journey to create a future where technology drives positive change and equality for all.,

The Common Hardware Group (CHG) at Cisco is responsible for delivering silicon, optics, and hardware platforms for the core Switching, Routing, and Wireless products. We design networking hardware for Enterprises, Service Providers, the Public Sector, and Non-Profit Organizations worldwide. Cisco Silicon One is a unique silicon architecture that allows customers to utilize top-of-the-line silicon in TOR switches, web-scale data centers, and across various networks with a unified routing and switching portfolio. Join our team and contribute to shaping Cisco's innovative solutions by participating in the design, development, and testing of cutting-edge ASICs. As a member of our team, you will be involved in the Verilog RTL and scripted flow implementation of Hardware Design-for-Test (DFT) features supporting ATE, in-system test, debug, and diagnostics requirements. Additionally, you will collaborate on Verilog testbench implementation for verification tests related to DFT features and use cases. Your role will also include contributing to automation scripts aimed at enhancing implementation quality and efficiency. **Minimum Qualifications:** - Bachelor's or Master's Degree in Electrical or Computer Engineering with a minimum of 2 years of experience - Knowledge of the latest trends in DFT, test, and silicon engineering - Proficiency in JTAG protocols, Scan and BIST architectures, including memory BIST and boundary scan - Familiarity with ATPG and EDA tools such as TestMax, Tetramax, Tessent tool sets, and PrimeTime - Verification skills encompass System Verilog Logic Equivalency checking and validating the Test-timing of designs **Preferred Qualifications:** - Understanding of VLSI circuit physical behaviors in silicon, including electrical migration and temperature/voltage effects - Knowledge of basic timing concepts like setup and hold, metastability - Experience with EDA tools - Strong verbal communication skills and ability to excel in a dynamic environment - Proficiency in scripting/coding languages like Tcl, Python, Perl, or C/C++ Cisco is a diverse and inclusive environment where individuality is celebrated, and collaborative teamwork drives meaningful change for an inclusive future. Embracing digital transformation, we assist our customers in implementing digital changes in their businesses, showcasing our expertise as both a hardware and software company. Our innovative network solutions adapt, predict, learn, and protect, setting us apart as a company that defies traditional categorization. At Cisco, we value accountability, boldness, and diversity of thought. We foster a culture of innovation, creativity, and learning from failures, all while promoting equality for all individuals. Our inclusive environment encourages employees to be themselves, whether it's through unique personal styles or a passion for technology and positive change. Join us at Cisco, where your individuality and dedication to excellence are celebrated.,

MTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs.?As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning PREFERRED EXPERIENCE: Understanding of DesignforTest methodologies and DFT verificationexperience (eg.IEEE1500, JTAG 1149.x, Scan, memory BISTetc.) Experience with Mentortestkompressand/or SynopsysTetramax/DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering