Developing emulation solutions for industry-standard protocols such as AXI, AMBA, JTAG, AVB, CAN, and TSN, CHI, Ethernet, PCIe, CXL, UCIe CSI, DSI, DP, UFS, MMC, HDMI, DRAM. Engaging in software development using C/C++ and synthesizable RTL development using Verilog. Verifying emulation solutions to ensure they meet the highest standards of quality and performance. Interacting with customers during the deployment and debugging phases to provide technical support and ensure successful implementation. Collaborating with cross-functional teams to integrate emulation solutions with other Synopsys products and technologies. Continuously improving and optimizing emulation solutions to meet evolving industry needs and standards. The Impact You Will Have: Enhancing the efficiency and performance of semiconductor design processes through advanced emulation solutions. Contributing to the development of high-performance silicon chips and software content that drive technological innovation. Supporting semiconductor customers in overcoming design and verification challenges, leading to successful product launches. Improving the reliability and functionality of emulation solutions, thereby increasing customer satisfaction and trust in Synopsys products. Driving continuous improvement and innovation within the emulation solutions domain. Facilitating seamless integration of emulation solutions with other Synopsys technologies, enhancing overall product offerings. What You'll Need: Strong programming skills in C/C++ and understanding of OOPS concepts. Good understanding of digital design concepts. Knowledge of HDL languages such as System Verilog and Verilog. Experience with scripting languages like Perl or TCL is a plus. Understanding of ARM architecture is an added advantage. Knowledge of UVM and functional verification will be a plus.

Design oriented and forward-looking thought process Sound knowledge of custom Analog/AMS design techniques, implementation and verification B.Tech. or M.Tech. degree in Electrical Engineering with 5+ years of relevant industry experience or Phd with relevant experience. Awareness of full custom layout techniques Exposure to advanced process challenges, including ESD and Reliability Exposure to architecture, design and verification of PVT, Oscillators, Bandgap, PLLs, LDOs, ADCs, Amplifiers, PHYs and other Mixed-signal blocks Excellent teamwork, communication, mentoring, and interpersonal skills with both internal teams and external customers Preferred skills : Strong custom design experience - specification, circuit design description and schematics Hands on experience with circuit design & simulation tools, IC design CAD packages - from any EDA vendor Strong understanding of SPICE simulator concepts and simulation methods Familiar with circuit simulation tools like PrimeSim, FineSim, HSPICE or similar Must have prior experience with Custom Compiler or equivalent schematic & Layout editor tools Experience with statistical design methodology like generating and analyzing Monte-Carlo results Awareness of post-layout extraction & simulation, testing in conjunction with silicon validation Demonstrated technical expertise in the productization of advanced technologies

Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You'll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. In-depth understanding of cache coherency protocols such as Protocol experience: Should have experience in any of the protocols, UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol. Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs. Proficiency in writing scripts using Perl, Python, and Shell scripting.

Providing expertise for test solutions during design planning, budgeting, and implementation. MBIST implementation and validation, including BIST architecture planning, memory grouping, pattern generation, validation, silicon bring-up, diagnostics analysis, and debug. Participating in customer s design and flow reviews. Driving, prototyping, and developing new Design for Test methodologies. Multitasking across various issues and priorities to help customers exploit new technologies. Collaborating with Solution Architects to develop and productize next-gen test technologies. The Impact You Will Have: Enhancing Synopsys ability to deliver cutting-edge test solutions that meet customer needs. Contributing to the successful integration and silicon bring-up of complex digital ICs. Ensuring high customer satisfaction through effective technical support and problem resolution. Driving innovation in test methodologies and technologies. Supporting the development of next-gen test technologies that push the boundaries of whats possible. Playing a key role in winning new customers and expanding Synopsys market presence. What You ll Need: Minimum BS+10 years of relevant experience/MS+8 years of relevant experience in Electrical Engineering, Computer Engineering, or other relevant fields of study. Experience with RTL coding, DFT insertion, ATPG, MBIST architecture planning, insertion, validation, pattern generation, and silicon bring-up. Excellent knowledge of memory BIST flows, memory fault models, MBIST algorithms, hard/soft repair, and eFuse repair flow. Experience in handling memory BIST for large, complex SoCs with various IPs. Exposure to MBIST of automotive designs is a plus. Good understanding of protocols like 1149.1, 1500, 1687.

What You ll Be Doing: Collaborate with cross-functional teams to develop and implement layout designs for analog and mixed-signal (A&MS) integrated circuitsin PLL and other IP Create and optimize layout designs using industry-standard EDA tools. Perform physical verification and design rule checks to ensure design integrity and manufacturability. Define, design and develop complex RF clock path Participate in design reviews and provide feedback to improve design quality. Work closely with circuit designers to understand design specifications and constraints. Contribute to the development and enhancement of layout design methodologies and best practices. Stay updated with the latest industry trends and advancements in A&MS layout design. The Impact You Will Have: Ensure the highest quality and performance of our analog and mixed-signal integrated circuits. Drive innovation by developing cutting-edge layout designs that push the boundaries of technology. Enhance the manufacturability and reliability of our products through meticulous design and verification processes. Contribute to the overall success of our projects by providing valuable feedback during design reviews. Improve design methodologies and best practices, fostering a culture of continuous improvement. Support the growth and development of junior engineers by sharing your expertise and knowledge. What You ll Need: Bachelors or Masters degree in Electrical Engineering or a related field. 7+ years of experience in A&MS layout design for integrated circuits. Hands physical design experience of passive elements used in PLL RC filter, LC oscillator Basic knowledge of PLL operating blocks Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, and methodologies. Experience with physical verification tools, such as Calibre or Assura. Understanding of semiconductor process technologies and their impact on layout design. Excellent problem-solving and systematic skills. Ability to work effectively in a team-oriented env Who You Are: Innovative thinker with a passion for technology and problem-solving. Excellent communicator, capable of articulating complex concepts clearly. Detail-oriented with a strong focus on quality and precision. Collaborative team player who thrives in a dynamic work environment. Adaptable and able to manage multiple priorities effectively

What You ll Need: Bachelors, Masters, or Ph.D. in Computer Science or a related field. At least 8 years of experience in GPU optimization and implementation. Advanced knowledge of CUDA or similar technologies. Proficiency in C/C++, Python, and distributed computing environments. Strong understanding of algorithms and data structures.

Expertise in UVM and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective. Locally should be to be go-to person on all technical aspects of VIP At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683Aschheim, GermanyEngineering Principal Analog Design EngineerMississauga, CanadaEngineering Verdi InternshipHsinchu, TaiwanInterns/Temp

What You ll Be Doing: Manage security-focused projects, ensuring alignment with organizational goals and industry standards. Oversee security initiatives related to open-source projects, including assessing vulnerabilities, coordinating remediation efforts, and promoting best practices within the engineering teams. Collaborate closely with stakeholders to define project objectives, scope, and deliverables. Develop and maintain comprehensive project plans. Drive effective communication and collaboration across cross-functional teams. Monitor program progress and implement solutions to keep projects on track. Drive continuous improvement initiatives by evaluating current processes and recommending enhancements to increase efficiency and security effectiveness. Proactively identify challenge areas and risks requiring executive engagement. Identify issues and roadblocks, and escalate with the right level of details and priority. Drive problem resolution through fact-based, conscious, and quality decision-making. The Impact You Will Have: Ensure the security and integrity of Synopsys products, particularly in open-source environments. Lead the initiatives w.r.t product security. Develop strategic project plans that align with organizational goals and industry standards. Facilitate cross-functional collaboration to enhance communication and project outcomes. Implement solutions to keep projects on track, ensuring timely delivery and high-quality results. Promote best practices and continuous improvement initiatives within the engineering teams. Identify and mitigate risks, ensuring proactive management of potential challenges. Provide valuable insights and recommendations based on data analytics, driving enhancements in product security. Foster a culture of security awareness and compliance within the organization. Contribute to the overall success of Synopsys security and data engineering initiatives. What You ll Need: Project Management Experience: 2+ years of experience specifically in technical program management with overall experience of 8 to 12 years. Hands-on working knowledge in Python / Perl. Ability to do code reviews and take part in design discussions. Product Security Knowledge: Strong understanding of product security principles, especially related to open-source projects. Experience with cloud platforms such as AWS, Azure, or Google Cloud. Communication skills: Excellent verbal and written communication abilities for cross-functional collaboration. Stakeholder Management: Ability to define project objectives and collaborate closely with stakeholders. Project Planning: Skills in developing and maintaining comprehensive project plans. Who You Are: A proactive and detail-oriented leader who can manage complex projects and drive them to successful completion. An excellent communicator who can effectively collaborate with cross-functional teams and stakeholders. A strategic thinker with a strong understanding of product security and data engineering principles. A problem solver who can identify challenges and implement effective solutions. A continuous learner who stays updated with the latest industry trends and best practices.

What You ll Be Doing: Optimize Linux-based systems to support critical operations. Oversee the design, implementation, and management of storage solutions. Monitor cluster performance and ensure efficient resource utilization using IBM LSF. Develop, test, and maintain Python scripts for automation, system monitoring, and infrastructure optimization. Collaborate with underwriting teams to understand and support their infrastructure requirements. Participate in capacity planning and disaster recovery exercises. The Impact You Will Have: Ensure the reliability and efficiency of our Linux-based systems, supporting critical operations. Design and manage robust storage solutions that meet the needs of our growing infrastructure. Optimize resource utilization and cluster performance, contributing to overall system efficiency. Automate routine tasks and system monitoring, enhancing operational efficiency. Provide vital support to underwriting teams, ensuring their infrastructure needs are met effectively. Contribute to strategic capacity planning and disaster recovery efforts, ensuring business continuity. What You ll Need: Deep understanding of Linux-based environments. Expertise in storage technologies (SAN, NAS, Object Storage, etc.). Hands-on experience with IBM LSF for workload management and troubleshooting. Proficiency in Python, with experience writing scripts for automation and system management. Strong analytical and troubleshooting skills in a complex, distributed environment. Who You Are: You are a collaborative team player with excellent communication skills. You are proactive, detail-oriented, and capable of managing multiple tasks simultaneously. Your ability to adapt to new technologies and environments, along with your commitment to continuous learning, sets you apart. You bring a positive attitude and a problem-solving mindset to every challenge you face. The Team You ll Be A Part Of: You will join a dynamic team of engineers focused on optimizing and managing our infrastructure. Our team is dedicated to supporting the computational requirements of various departments, ensuring that our systems are robust, efficient, and scalable. We value innovation, collaboration, and continuous improvement, and we are committed to fostering a supportive and inclusive work environment. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683Aschheim, GermanyEngineering Principal Analog Design EngineerMississauga, CanadaEngineering Verdi InternshipHsinchu, TaiwanInterns/Temp

Requirements At-least 5+ years of experience in Physical Implementation RTL-GDS. Experience in independently debugging and resolving Synth &PnRimplementation challenges. Ability to handle complete project independently through timely successful outcome.. Candidate must have good exposure towards methodology changes to achieve targeted PPA metrics for complex designs. Proficiency in Synopsys implementation tools is an advantage The individual must be self-motivated and dedicated with strong debug skills Requires proficiency in scripting (tcl/unix/perl) Excellent communication skills including ability to interface with customers and business unit personnel are essential.

What You ll Need: Relevant Bachelors or Masters degree. 5+ years of software development/deployment experience. Cloud certifications (AWS, GCP, Azure). 3-5 years of DevOps experience. Experience with Linux and Windows. Scripting skills (Bash, Python, Perl). CI/CD tools proficiency (GitHub, GitLab, Bitbucket). Containerization and orchestration experience (Docker, K8s). Ansible and Jenkins automation skills. Proficiency with DevOps tools (JIRA, Confluence, Jenkins).

You are a highly skilled and motivated Test Automation Engineer with 7 to 10 years of experience in test automation for software applications, APIs, Data/AI stacks, web applications, and open-source components integration in cloud and on-prem environments. You have a robust understanding of Kubernetes and containerized ecosystems, and hands-on experience in Linux environments. You are proficient in programming languages such as Python, Java, or JavaScript and familiar with modern CI/CD tools and cloud platforms like AWS, Azure, or Google Cloud. Your strong analytical skills, attention to detail, and proactive problem-solving abilities make you a valuable team player. You are adaptable, eager to learn new technologies, and possess excellent communication skills. Relevant certifications in test automation, Data/AI architectures, and cloud platforms would be a significant plus. What You ll Be Doing: - Design, develop, and maintain automated test scripts for cloud and on-prem software applications, APIs, data stacks, and web applications. - Collaborate with cross-functional teams to define and implement test strategies and ensure comprehensive test coverage. - Execute and analyze automated test results and coordinate with development teams to resolve identified issues. - Design and conduct performance testing of specific stack components to identify bottlenecks and suggest improvements. - Document and report test results, progress, challenges, and solutions to internal stakeholders. - Perform DevOps tasks as necessary to support a robust and scalable test environment. - Stay current with industry best practices, emerging tools, and technologies to continuously improve testing processes and outcomes. The Impact You Will Have: - Enhance the reliability and performance of Synopsys cloud and on-prem software applications. - Improve the efficiency of our development and testing processes through automation. - Contribute to the delivery of high-quality, robust software products to our clients. - Identify and resolve bottlenecks, ensuring optimal performance of our software solutions. - Provide valuable insights and recommendations to enhance our testing frameworks and strategies. - Support the scalability and robustness of our test environments through effective DevOps practices. What You ll Need: - Bachelor s degree in computer science, Software Engineering, or a related discipline. - 5 to 10 years of experience in test automation for cloud-based software applications, APIs, data stacks, and web applications. - Experience with key automation tools and frameworks (e.g., Selenium, JUnit, TestNG, Postman, Zephyr, Robot Framework). - Solid understanding of Kubernetes and containerized ecosystems (e.g., Docker, Singularity). - Hands-on working experience in Linux (e.g., CentOS). - Proficiency in programming languages such as Python, Java, or JavaScript. - Familiarity with modern CI/CD tools (e.g., Jenkins, GitLab CI, CircleCI). - Experience with cloud platforms (e.g., AWS, Azure, Google Cloud). - Competence in evaluating modern data and AI stacks. Who You Are: - Collaborative team player with strong communication skills. - Analytical thinker with a keen attention to detail. - Proactive problem-solver with excellent troubleshooting abilities. - Adaptable and eager to learn new technologies and methodologies. - Relevant certifications in test automation, Data/AI architectures, and cloud platforms. - Strong familiarity with database technologies and SQL. - Familiarity with data engineering tools such as Kafka, Spark, Dask, Hive, Airflow, SQL and NoSQL databases, and in-memory databases such as Redis. - Knowledge of on-prem data center networking is a plus. The Team You ll Be A Part Of: You will be part of a dynamic team focused on ensuring the quality and performance of Synopsys software products. The team collaborates closely with development, operations, and product management to deliver high-quality solutions that meet the needs of our customers. Your contributions will directly impact the success of our software applications and the satisfaction of our clients. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683Aschheim, GermanyEngineering Principal Analog Design EngineerMississauga, CanadaEngineering Verdi InternshipHsinchu, TaiwanInterns/Temp

What Youll Need: 8+ years of relevant experience, Results-driven mindset, Exposure to large design emulation compiles along with advanced protocols like PCIe and DDR interfaces, Experience with Zebu in the context of technology and SW validation, Proven track record in product deployment, specifically emulation, Experience in cross-functional collaborations, Excellent communication skills and a beacon for change, Adaptability and comfort in a matrixed, international environment,

What You ll Be Doing: Understanding design specifications, defining verification scopes, developing test plans, tests, and verification infrastructure. Implementing and analyzing System Verilog assertions and coverage (code, toggle, functional). Collaborating with other verification team members to develop and execute verification test cases. Leading and mentoring junior engineers, helping them debug complex problems. Working with architects, designers, and pre- and post-silicon verification teams to accomplish tasks. Adhering to quality standards and best verification practices. Ramping up on new verification tools and methodologies using Synopsys products to enable customers. Developing innovative solutions to problems independently. Setting task-level goals and consistently meeting schedules. Collaborating with other Synopsys teams, including BU AEs and Sales, to develop and deploy tool and IP solutions. The Impact You Will Have: Ensuring the correctness and reliability of complex SoC designs. Enhancing the efficiency and effectiveness of verification processes. Mentoring and developing the skills of junior engineers. Contributing to the successful delivery of high-quality SoC products to market. Driving innovation in verification methodologies and tools. Strengthening Synopsys position as a leader in the semiconductor industry through your technical expertise. What You ll Need: B.E/B. Tech/M. E/M. Tech in electronics with 4-8 years of experience in the verification domain. Experience in IP level or SoC level verification. Proficiency in processor-based SoC level verification, including Verilog, System Verilog, and UVM. Hands-on experience with verification tools such as VCS and waveform analyzers. Experience with third-party VIP integration (e.g., Synopsys VIPs). Proficiency in UVM, C/C++, and System Verilog verification languages. Understanding of AXI-AMBA protocol variants. Experience with scripting languages (shell, Makefile, Perl). Strong understanding of design concepts and ASIC flow. Strong problem-solving, analytical, and debugging skills. Experience with ARM core verification and ARM-based technologies. Experience with USB, PCIe, and MIPI protocols. Excellent communication skills. Who You Are: An innovative thinker with a passion for technology and verification. A collaborative team player who excels in dynamic environments. An excellent communicator who can articulate complex ideas clearly. A problem solver with a keen eye for detail and quality. A mentor and leader committed to developing the skills of junior engineers. A lifelong learner dedicated to staying at the forefront of technological advancements.

Required Qualifications: Bachelor with 4 years experience or MSEE (or PhD) with 2 years experience in Electrical Engineering, Computer Engineering, or similar technical field In-depth familiarity with transistor level circuit design - sound CMOS design fundamentals. Silicon-proven experience implementing circuits for the TX, RX and Clock paths within a SerDes Detailed design experience with several of the following SerDes sub-circuits: receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects. Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.). Experience with EDA tools for schematic entry, physical layout, and design verification. High proficiency with spice simulators including HSPICE, Finesim and XA Knowledgeable in Verilog-A and/or System-Verilog for analog behavioral modeling and simulation-control / data-capture. Plus Qualifications: Ability to provide automation for rapid and dynamic design needs is highly sought-after Experience with STA and cell characterization such as Nanotime, Primetime, SiliconSmart Experienced in STAR or similar extractor to debug extraction issues Extensive programming skills in languages such as Python, Perl, TCL and C/C++

Developing Sign Off ECO optimization algorithms and heuristics. Debugging issues related to design loading and timing/power optimization. Striving for continuous improvements in QoR to achieve faster timing convergence with optimal power overhead. Collaborating with a team of engineers to develop technical solutions to complex problems. Communicating with product engineers to understand and define problem scope. Ensuring strict performance and quality requirements are met. The Impact You Will Have: Enhancing the performance and efficiency of PrimeClosure, the industrys first AI-driven signoff ECO solution. Contributing to the development of cutting-edge algorithms that optimize timing and power in chip design. Improving the overall quality and reliability of our products through rigorous debugging and testing. Driving innovation and continuous improvement in our engineering processes. Supporting customer success by resolving issues and implementing new features based on their feedback. Helping shape the future of AI-driven optimization in the semiconductor industry. What You ll Need: A degree in Computer Science or Electronics. 5+ years of experience in relevant field Strong analytical and problem-solving skills. Proficiency in C/C++ and Linux. Excellent communication and teamwork abilities. A passion for technology and innovation. Who You Are: A collaborative team player who thrives in a dynamic and innovative environment. A proactive and self-motivated individual with a strong attention to detail. An excellent communicator who can articulate complex ideas clearly and effectively. A creative thinker who is always looking for new ways to solve problems and improve processes. A dedicated professional committed to delivering high-quality work

You Are: As a new, exciting, and challenging position, we are looking for a talented person that can show a great level of initiative and ability to work in a busy and fast-changing environment. This rewarding role is fundamental to the successful and smooth operation of the engineering teams. You will play a vital role in helping to strengthen and develop forecasting capabilities, based upon improved monitoring capacity and forward-looking project schedules. Contribute to the development and enhancement of layout design methodologies and best practices. Work closely with different function design leaders to understand/enhance processes and help to enhance methodology. Collaborate with internal infrastructure teams on compute grid, storage management, and job scheduling architecture, efficiency, maintenance, and forecasting. Understanding CAD infrastructure and methodology will help to set up project environments. Contribute to enhancing quality assurance methodology by adding more quality checks/gatings. Front End development process understanding and support internal tools development and automation to help improve productivity across ASIC design cycles. Work with design engineers on new tools/technology and new features evaluation and adoption. Perform physical verification and design rule checks to ensure design integrity and manufacturability. Stay updated with the latest industry trends and advancements in A&MS layout design. Understanding of tools like VC Spyglass, Verdi, & views like SDF, Liberty, etc., and other frontend views will add value to this position. Writing RTL Code and TCL is a good addition. The Impact You Will Have: Enhance layout design methodologies and best practices, contributing to the overall quality and efficiency of the design process. Improve project forecasting capabilities by leveraging advanced monitoring and scheduling techniques. Boost productivity across ASIC design cycles through the development and automation of internal tools. Ensure design integrity and manufacturability through meticulous physical verification and design rule checks. Stay at the forefront of industry advancements, bringing the latest trends and technologies into Synopsys design practices. Collaborate effectively with cross-functional teams, driving innovation and continuous improvement in design methodologies. What You ll Need: Bachelor s or master s degree in engineering or a related field. 2 to 3+ years of experience in A&MS frontend and backend views & collaterals development flows. Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, and methodologies. Experience with physical verification tools, such as Calibre or Assura. Understanding of semiconductor process technologies and their impact on layout design. Excellent problem-solving and systematic skills. Ability to work effectively in a team-oriented environment. Familiarity with Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV). Good communication and interpersonal skills.

As a new, exciting, and challenging position, we are looking for a talented person that can show a great level of initiative and ability to work in a busy and fast-changing environment. This rewarding role is fundamental to the successful and smooth operation of the engineering teams. You will play a vital role in helping to strengthen and develop forecasting capabilities, based upon improved monitoring capacity andforward-looking project schedules. You will generate test benches and test cases, perform RTL and gate-level SDF-annotated simulations and debug, and may perform mixed-signal (digital + analog) simulations and debug. You will interact with our application engineers and provide guidance to customers. Additionally, you will participate in the generation of data books, application notes, and white papers. What You ll Be Doing: Generate test benches and test cases. Perform RTL and gate-level SDF-annotated simulations and debug. May perform mixed-signal (digital + analog) simulations and debug. Interact with our application engineers and provide guidance to customers. Participate in the generation of data books, application notes, and white papers. Perform physical verification and design rule checks to ensure design integrity andmanufacturability. Understand tools like VC Spyglass, Verdi, & views like SDF, Liberty, etc., and other frontend views. Write RTL Code, with solid Verilog, PERL, and Python skills, and TCL is a good addition. Understand static timing analysis and synthesis, DFT/ATPG skills would be a plus. Knowledge of any high-speed communication protocol is not mandatory but an asset. Previous knowledge in customer support and/or silicon bring-up is a plus. The Impact You Will Have: Strengthen and develop forecasting capabilities based on improved monitoring capacity. Ensure high-quality and reliable silicon lifecycle monitoring solutions. Enhance quality assurance methodology by adding more quality checks/gatings. Support internal tools development and automation to improve productivity across ASIC design cycles. Work with design engineers on newtools/technology and new features evaluation and adoption. Contribute to the successful and smooth operation of the engineering teams. What You ll Need: Bachelor s or master s degree in electrical engineering or a related field. 3 to 7+ years of experience in A&MS frontend and backend views & collaterals development flows. Proficiency inindustry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, andmethodologies. Experience with physical verification tools, such as Calibre or Assura. Understanding of semiconductor process technologies and their impact on layout design. Who You Are: Excellentproblem-solving and systematic skills. Ability to work effectively in a team-oriented environment. Familiarity with Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV). Good communication and interpersonal skills.

This challenging position will offer you the opportunity to work with Synopsys advanced technology in a collaborative environment to: Develop validation environment on various industry-based SoC design on Emulation/FPGA and/or Virtual environments. Collaborate with Design SoC, Solutions and Synopsys IP team. Collaborate across complementary teams to develop and trace system requirements, functionality and Performance environment. Align with the development work taking place across multiple teams. This includes steering the development of functional and performance test plans, environment and supporting the Emulation/FPGA,Solutions and IP team. Stay up to date with the latest advancements in semiconductor design and Emulation technology to drive innovation and continuous improvement. Mentor to junior engineers and team members Work with engineering teams to improve various workloads Required Skills & Experience: Bachelor s or Master s in Electronic Engineering, Electrical Engineering, Computer Engineering, VLSI, or related field. Minimum 8 years in SoC Validation. Have emulation experience in Zebu/Haps or equivalent platforms. Have HW RTL verification and debugging expertise. Design & Develop test environment having various debug hooks and automation. High speed protocols (such as USB, PCIe, UFS or LPDDR technology)knowledge/experience is a plus. Able to work independently with minimal supervision, Lead the team technically, Capable of mentoring and developing a strong team. Nice To Have Skills & Experience: Excellent communication (written, verbal, presentation) skills. Proven track record of generating consistent, complete, and concise written specifications. Motivated to continuously develop skills, development processes, and improve results At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share

Supporting development and verification of ASIC digital designs for next-generation NRZ and PAM-based SerDes products. Setting up and running lint/cdc/rdc checks using VC-Spyglass and synthesis flow using Design Compiler/Fusion Compiler. Working with Verilog and VCS to ensure design accuracy. Defining synthesis design constraints and resolving STA issues. Setting up and running FPGA prototyping flows to map RTL designs to Xilinx FPGAs. The Impact You Will Have: Contributing to the development of cutting-edge SerDes products that lead the industry. Enhancing the performance, power, and size efficiency of our silicon IP offerings. Enabling rapid market entry for differentiated products with reduced risk. Driving innovation in high-speed digital design and data recovery circuits. Supporting the creation of high-performance silicon chips and software content. Collaborating with a world-class team to solve complex design challenges. What You'll Need: BSEE or MSEE with a minimum of 2 years of experience in digital design and front-end flows. Proficiency in running lint/cdc/rdc checks and synthesis flow. Experience in coding, verifying Verilog and System Verilog design. Experience of working with minimum supervision and owning and delivering for front-end activities in IP/SOC. Experience of leading technically for front-end activities. Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows. Scripting experience in Shell, Perl, Python, and TCL (preferred). Who You Are: Excellent communicator with the ability to interact with diverse teams. Self-motivated and proactive, with a strong attention to detail. A creative problem-solver who can think independently. Capable of working under tight deadlines while maintaining high-quality standards. A team player who can contribute effectively both individually and collaboratively