Working on functional verification of high-speed serial link PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Studying IP/design blocks/firmware specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs) as per verification plan needs. Performing simulation, random and direct stimulus development, and coverage review. Working closely with digital designers for debugging and achieving the desired coverage. The Impact You Will Have: Ensuring the accuracy and functionality of high-speed interface IPs, contributing to the development of cutting-edge technology. Enhancing the reliability and performance of Synopsys products through meticulous verification processes. Driving innovation in the semiconductor industry by verifying complex digital designs. Collaborating with a team of skilled professionals to deliver high-quality IPs that meet industry standards. Improving the efficiency of the verification process through automation and advanced verification methodologies. Contributing to the overall success of Synopsys by ensuring the delivery of robust and reliable IPs to customers.

You are a seasoned professional in RTL Design and Signoff , bringing a wealth of experience and expertise to the table. You have a keen understanding of the complexities of RTL Quality Signoff and are adept at proposing resource requirements to meet project goals. Your leadership skills are top-notch, allowing you to guide a team of engineers through various pre-silicon static verification activities on IPs/Subsystems . You have a strong grasp of design and architecture , enabling you to develop precise timing constraints for synthesis and timing . Your ability to ramp up on new RTL Design and Static Verification tools and methodologies using Synopsys Products ensures that you stay ahead of the curve. You collaborate effectively with peers to enhance methodology and execution efficiency. Your excellent communication skills facilitate smooth interactions with Synopsys customers, BU AEs, Sales teams, and other stakeholders. With a minimum of 8+ years of experience , you are well-versed in debugging, diagnosing violations, and setting up flows and methodologies for quick RTL Signoff tool deployment . Your technical expertise in LINT, CDC, RDC, and timing constraints development is unparalleled. You are a strategic thinker with a strong understanding of design concepts, ASIC flows, and stakeholder management . What You'll Be Doing: Work with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities. Understand the complexity and requirements of RTL Quality Signoff and propose resource requirements to complete the activities. Lead a team of engineers to perform various pre-silicon static verification activities on IPs/Subsystems. Develop timing constraints for synthesis and timing while understanding the design/architecture. Collaborate with peers to improve methodology and enhance execution efficiency. Ramp up on new RTL Design and Static Verification tools and methodologies using Synopsys Products to enable customers. Work with other Synopsys teams, including BU AEs and Sales, to develop, broaden, and deploy Tool and IP solutions. Set up flows and methodologies to enable quick setup for RTL Quality checks, Synthesis, and Formality. Train the team in design concepts and root-cause analysis. The Impact You Will Have: Ensure high-quality RTL Signoff and design, contributing to the success of Synopsys projects. Lead the team in delivering precise and efficient pre-silicon static verification activities. Enhance the overall execution efficiency of RTL Design and Signoff processes. Enable customers to achieve their goals through the deployment of Synopsys Products and methodologies. Develop and implement innovative solutions for RTL Quality Signoff in the semiconductor industry. Strengthen Synopsys reputation as a leader in chip design, verification, and IP integration. What You'll Need: B.E/B.Tech/M.E/M.Tech in electronics with a minimum of 8+ years experience in RTL Design and Verification. Technical expertise in various aspects of RTL Design and Signoff: LINT, CDC, RDC. Technical expertise in setting up flows and methodologies for quick deployment of RTL Signoff tools. Technical expertise in debugging and diagnosing violations and errors. Technical expertise in developing timing constraints and running preliminary synthesis for timing constraints check and area estimation. Ability to lead a team to perform RTL Signoff on complex SoC/IP/Subsystem. Experience with planning and managing various activities related to RTL Signoff and Design. Strong understanding of design concepts, ASIC flows, and stakeholders. Good communication skills.

You are a seasoned professional with a robust understanding of project and program management. You have a knack for driving the on-time delivery of patches and releases for small products and can assist with larger product releases. You possess excellent interpersonal and communication skills, enabling you to interface seamlessly between R&D, DevOps, management, and Application Engineers. You bring a wealth of experience in software development, particularly in C/C++, and have an in-depth knowledge of project management concepts. Your passion for customer focus and quality is evident in your work, and you are always on the lookout for tools and automation to improve productivity and quality. You thrive in a process-oriented environment, are confident in handling conflicting situations, and can work effectively across multiple teams and geographies. Your background in the EDA domain and knowledge of configuration management tools and Unix environments make you a valuable asset. With over 5 years of relevant experience in program management, process and releases, or software development, you are ready to take on new challenges and drive success for Synopsys. What You'll Be Doing: Take ownership and drive on-time delivery of patches and releases for small products. Assist other Release Managers on larger products and assignments. Independently drive commitments and convergence of patches and releases as per established processes, welcoming new ideas. Act as the interface between R&D, DevOps, management, and Application Engineers. Utilize excellent interpersonal, communication, and follow-up skills to ensure team collaboration and success. Apply hands-on experience in C/C++ software development to enhance project outcomes. What You'll Need: Hands-on experience in C/C++ software development. In-depth knowledge of program management concepts. Experience with Perforce, Perl, Shell scripts, Python, Make, and other industry-standard configuration management tools. Proficiency in Unix environments. 5+ years of relevant experience in program management, process and releases, or software development. Excellent academic background with a B.E./B.Tech/M.Tech in Computer Science, Electrical, or Electronic Engineering from reputed universities. Who You Are: Process-oriented and confident in handling conflicting situations. Flexible, resourceful, and responsible in completing assigned tasks. Passionate about customer focus and quality. Enthusiastic about trying new tools and automation for productivity and quality improvements. Experienced in multi-team, cross-geography product delivery.

What You ll Be Doing: Develop and review the verification test-plan for multi-protocol 112G PHY IP sub-system of Controller/MAC+PCS+PHY. Create and optimize the verification environment based on UVM. Verify the inter-operability of Controller/MAC, PCS, with PHY of different Tech nodes. Execute RTL simulations, Gate Level Simulations, and ensure coverage closure (Functional + Code). Deliver high-quality RTL and Simulation models to customers. Coordinate between RTL, Analog design, and Tech pub teams. Support customers with the integration and bring-up of IP in their simulation environments. Develop and deliver SV verification components for customer integration. Assist customers with silicon bring-up and debug issues when customer silicon is available. The Impact You Will Have: Ensure the delivery of robust and high-quality verification solutions for Synopsys high-performance PHY IPs. Drive innovation and efficiency in verification processes, contributing to the advancement of cutting-edge technologies. Enhance customer satisfaction through exceptional support and high-quality deliverables. Facilitate the seamless integration of Synopsys IPs into customer designs, ensuring successful product launches. Contribute to the development of industry-leading verification methodologies and best practices. Help maintain Synopsys reputation as a leader in chip design and verification solutions. What You ll Need: B.Tech/M.Tech with 7+ years of relevant experience. Proficiency in interface protocols such as Ethernet, PCIe, CXL, JESD, and CPRI. Experience with functional verification flow, Verification tools, and methodologies VMM, OVM/UVM, and System Verilog. Expertise in Gate Level Simulation with SDF, System Verilog Assertions, and coverage implementation. Fundamental knowledge of Analog and Digital mixed signal design. Proficiency in scripting and automation using TCL/Perl/Python. Excellent debug and diagnostic skills.

What You ll Need: Education: Bachelor s degree in engineering, Computer Science, or related field. Experience: Minimum 5 to 10 years of experience in project management, preferably in the technology industry. Certifications: PMP certification or equivalent. Skills: Strong project management skills, including planning, organizing, and controlling. Excellent communication and leadership skills. Ability to work in a fast-paced environment and adapt to changing priorities. Strong analytical and problem-solving skills. Experience with project management tools. Familiarity with Synopsys toolset (such as FC/ICC2, Primetime, Formality, ICV). Good communication and interpersonal skills.

Key Qualifications Must have B.Tech or M.Tech with 4-7 years of relevant experience. Good knowledge of Physical design , STA , Physical Verification and Parasitic Extractionmethodologies. Proficiency in Unix, a strong understanding of ASIC design flow. Knowledge of Analog Mixed Signal flows will be an added advantage. Strong communication skills are a must. Proficiency in scripting languages - shell scripting, tcl, python would be helpful

What you'll Be Doing: Leading Serdes analog design and development. Analyzing various mixed signal techniques for power reduction, performance enhancement, and area reduction. Developing Analog Full custom circuit macros for High Speed PHY IP in advanced technology nodes. Collaborating with silicon test and debug experts for Sim2Sil correlation. Building and nurturing a team of analog design talent. Working with experienced teams locally and globally. The Impact You Will Have: Driving innovation in mixed-signal analog design. Enhancing the performance and efficiency of high-speed physical interfaces. Contributing to the development of cutting-edge technology in High Speed PHY IP. Improving quality and reliability through collaboration and Sim2Sil correlation. Growing the business impact by building and leading a talented team. Advancing Synopsys leadership in chip design and IP integration. What you'll Need: BE 18+ years of relevant experience or MTech 15+ years of relevant experience in mixed signal analog, clock, and datapath circuit design. Strong knowledge of RF architecture and blocks such as transceivers, VCOs, LNA, and up/down converters. Experience in designing Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits. Proficiency in high-speed digital circuit design and timing/phase noise analysis. Ability to create behavioral models of PLL to drive architectural decisions. Who You Are: Strong fundamentals of CMOS, device physics, and sub-micron design methodologies. Experience with PLL designs and high-speed digital circuit design. Knowledge of control systems, band gaps, bias, op-amps, LDOs, and feedback techniques. Experience in LC VCO/DCO design and performance parameters of VCO. Familiarity with digitally assisted analog circuit techniques.

What You ll Need: BSEE or MSEE with a minimum of 4 years of experience in digital design and front-end flows. Proficiency in running lint/cdc/rdc checks and synthesis flow. Experience in coding, verifying verilog and system verilog design. Experience of working with minimum supervision and owning and delivering for Front end activities in IP/SOC Experience of leading technically for Front end activities. Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows. Scripting experience in Shell, Perl, Python, and TCL (preferred).

What You ll Need: BSEE or MSEE with a minimum of 4 years of experience in digital design and front-end flows. Proficiency in running lint/cdc/rdc checks and synthesis flow. Experience in coding, verifying verilog and system verilog design. Experience of working with minimum supervision and owning and delivering for Front end activities in IP/SOC Experience of leading technically for Front end activities. Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows. Scripting experience in Shell, Perl, Python, and TCL (preferred).

Requirements- Qualification: BTech/MTech Skills/Experience: MTech+3years / BTech+5years Knowledge of CMOS processes and issues in deep submicron process technologies. CMOS circuit design and layout methodology & flow; basic understanding of analog/mixed signal circuitry, familiarity with basic ESD concepts is an advantage. Familiarity with ASIC design flow. Knowledge of JEDEC requirements for DDR interfaces & standards, DDR Timing, ODT and SDRAM functionality would be a plus. Ability to execute assigned circuit design tasks with best product quality and efficiency. Good written and verbal communication skills in interactions with internal development teams.

Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You'll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. You will be responsible for functional verification involving coherent and non-coherent IP designs. Proficiency in writing scripts using Perl, Python, and Shell scripting.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: As a seasoned Software Engineering, Staff Engineer, you thrive in fast-paced environments and have a proven track record of delivering high-quality results You are proficient in both front-end and back-end development, with extensive experience in various programming languages and frameworks Your expertise in Linux platform and familiarity with common stacks enables you to build scalable and efficient systems You possess a deep understanding of CI/CD tools and have hands-on experience with automation scripts, enhancing testing efficiency and coverage Your ability to analyze complex technical problems and implement effective solutions makes you a valuable asset to any team You are committed to iterative development, continuous integration, and delivery, ensuring that projects are completed successfully With a Masters or Bachelors degree in computer science or a related field, and over seven years of experience as a Software Engineer, you are ready to take on new challenges and drive innovation at Synopsys, What Youll Be Doing: Follow design principles of software engineering and systems to build features that improve platform and tools availability, scalability, latency, and efficiency, Design and maintain test frameworks, including various tools to empower developers to automate test cases effectively, Develop, update, and manage automation scripts for various Infrastructure and application test case scenarios to enhance testing efficiency and coverage, Evaluate design approaches and tools, build frameworks, and improve existing systems, Set up CI/CD tools as part of the engineering efforts, Collaborate with cross-functional teams to drive productivity, robustness, agility, and time-to-market advantage in the creation of Synopsys products and solutions, The Impact You Will Have: Enhance the availability, scalability, latency, and efficiency of Synopsys platforms and tools, Empower developers with effective automation tools, improving testing efficiency and coverage, Drive significant productivity and robustness in the creation of Synopsys products and solutions, Lead corporate infrastructure transformation and IT operations leadership, Invest in the next wave of disruptive technologies to maintain Synopsys competitive edge, Contribute to the growth and scaling strategy of Synopsys through innovative solutions, What Youll Need: Ability to work in a high-performing team and balance high-quality delivery with customer focus to meet business needs, Prior experience as a Full Stack Developer or similar role, Experience working on Linux platform and familiarity with common stacks, Knowledge of multiple front-end languages and libraries (e-g , HTML/CSS, JavaScript, XML, jQuery), Knowledge of multiple back-end languages (e-g , Dot net, Java, Python, Ruby) and JavaScript frameworks (e-g , React, NodeDot JS), Familiarity with databases (e-g , MySQL, MongoDB), web servers (e-g , Apache), and UI/UX design principles, Experience working in an Agile development environment, with a commitment to iterative development, continuous integration, and delivery, Experience with build systems, CI/CD tools (like AWS DevOps, Jenkins), application analytics/monitoring, Experience with Artifactory, package managers including yum, rpm, and apt, Ability to analyze complex technical problems, troubleshoot issues, and implement effective solutions in a timely manner, Takes pride in working on projects to successful completion involving a wide variety of technologies and systems, Masters/Bachelors degree in computer science or related field of study and 7+ years of experience as a Software Engineer, Who You Are: Innovative thinker who is always looking for ways to improve systems and processes, Detail-oriented and committed to delivering high-quality results, Excellent communicator with the ability to collaborate effectively with cross-functional teams, Proactive problem solver who can troubleshoot and resolve issues efficiently, Adaptable and able to thrive in a fast-paced, dynamic environment, Passionate about technology and continuous learning, The Team Youll Be A Part Of: The Engineering Excellence Group drives innovation velocity and enterprise infrastructure automation, which are critical elements of our growth and scaling strategy This team is chartered to drive significant productivity, robustness, agility, and time-to-market advantage in the creation of Synopsys products and solutions The group also leads corporate infrastructure transformation as we continue to drive IT operations leadership and invest in the next wave of disruptive technologies, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

What You ll Need: Bachelors or Master s degree in Computer Engineering or a related field from a reputed institute. 8+ years of experience in C/C++ software development. Strong knowledge of job scheduling, Linux systems, Shell Scripting, and REST APIs. Experience with Electronic Design Automation (EDA) tools is highly desirable. Excellent problem-solving and analytical skills.

Main responsibilities Mentor a team of engineers, set goals for the team, and drive for results. Will drive quality improvement effort by understanding customer design methodologies/flows and validating our tools to meet the required metrics before they are released to the customer. Perform in depth customer incoming root cause analysis to understand the product areas that need improvement and execute proactive testing to reduce customer issues by improving product quality. Identify opportunities to automate and find innovative solutions to improve productivity of teams. Work directly with R&D, Product Engineers, Field Engineers & customers to suggest improvements in Signoff and validation. Use in-depth product understanding to provide technical expertise , diagnose, troubleshoot issues. Key Qualifications The ideal candidate should have domain knowledge in timing, statistical analysis, front-end/back-end semiconductor manufacturing BSEE or equivalent, required with 10-12 years of experience , or MSEE. Synopsys tools like PrimeTime, Siliconsmart, NanoTime, PrimePower and Library Compiler experience is important, PD experience is a bonus. Exceptional debugging skills with good understanding of scripting languages. Experience with mentoring individuals is required.

Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You'll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 10-15 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 9-12 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. You will be responsible for functional verification involving coherent and non-coherent IP designs. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol.

Your background in verification IP development and your programming prowess in languages like Perl, Python, and Shell scripting set you apart as a valuable asset to our team, What Youll Be Doing: Responsible for functional verification involving coherent and non-coherent IP designs, Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements, Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs, Developing verification plans and driving functional coverage-driven verification closure of real designs, Debugging and resolving issues in verification environments to ensure robust and reliable verification processes, The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes, Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols, Driving innovation in the automotive sector by developing robust verification solutions for automotive systems, Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices, Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements, Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products, What Youll Need: E/B Hands-on experience in architecting and building System Verilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs, In-depth understanding of cache coherency protocols such as Protocol experience: Should have experience with Display Port/HDMI/MIPI/USB/PCI-E protocol preferably the latest specifications Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs, Proficiency in writing scripts using Perl, Python, and Shell scripting, Who You Are: Excellent problem-solving, debugging, and analytical skills, Strong programming skills and familiarity with object-oriented programming concepts, Creative and innovative mindset, Excellent verbal and written communication skills, A collaborative team player with a passion for functional verification,

Your experience in architecting and building SystemVerilog UVM-based verification components, coupled with your expertise in cache coherency protocols and functional verification, makes you an ideal candidate for this role You are a team player with excellent problem-solving abilities, strong analytical skills, and a keen attention to detail Your background in verification IP development and your programming prowess in languages like Perl, Python, and Shell scripting set you apart as a valuable asset to our team, What Youll Be Doing: Responsible for functional verification involving coherent and non-coherent IP designs, Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements, Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs, Developing verification plans and driving functional coverage-driven verification closure of real designs, Debugging and resolving issues in verification environments to ensure robust and reliable verification processes, The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes, Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols, Driving innovation in the automotive sector by developing robust verification solutions for automotive systems, Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices, Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements, Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products, What Youll Need: E/B Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs, You will be involved in creating System verification solutions for Arm AMBA5 protocols such as CHI, AXI5/ACE5 for on-chip, chi-to-chip, die-to-die, coherent and non-coherent design topologies, You will be responsible for functional verification involving coherent and non-coherent IP designs, Proficiency in writing scripts using Perl, Python, and Shell scripting, Who You Are: Excellent problem-solving, debugging, and analytical skills, Strong programming skills and familiarity with object-oriented programming concepts, Creative and innovative mindset, Excellent verbal and written communication skills, A collaborative team player with a passion for functional verification,

Supporting the People team s digital transformation initiatives. Building and maintaining People tools, ensuring they meet organizational needs. Collaborating with various stakeholders to gather requirements and implement solutions. Providing expert guidance on People tools like ServiceNow HRSD and SuccessFactors to optimize their use. Collaborate with HR and IT teams to ensure seamless integration of People systems with existing enterprise applications. Design, develop, and implement automation workflows using tools such as RPA (Robotic Process Automation) software. Evaluate and implement AI-driven solutions to enhance HR functions, such as talent acquisition, employee engagement, performance management, and learning and development. Conducting regular system audits and troubleshooting issues as they arise. Training and supporting end-users to ensure they are proficient in using People tools. The Impact You Will Have: Enhancing the efficiency and effectiveness of HR processes through optimized People tools. Contributing to the successful implementation of digital transformation projects within the People team. Improving Employee and Manager experiences through systems. Ensuring data integrity and accuracy within our People systems. Facilitating better decision-making through improved data accessibility and reporting capabilities. Reducing system downtime by proactively identifying and resolving issues. Empowering team members with the knowledge and tools they need to succeed. What You will Need: Expertise in People systems like ServiceNow HRSD, SuccessFactors, Avature etc. Strong analytical and problem-solving skills. Excellent communication skills, both written and verbal. Experience in supporting digital transformation initiatives. Ability to conduct system audits and troubleshoot technical issues.

What You ll Need: Strong project management skills with 5+ years of experience. Solid background in project management and engineering. Experience with Jira, Confluence, and Microsoft Project Planner. Deep understanding of engineering principles and their application in real-world scenarios. Knowledge in automotive and functional safety development is an advantage.

What You ll Be Doing: Manage and lead a team of 7-8 SoC/Subsystem RTL Design Engineers for various customer engagements. Work with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities. Lead the team to perform various RTL Design and Signoff activities for SoC Subsystems such as SoC u-Architecture and Integration, RTL Design (Verilog/SystemVerilog), Lint, CDC, RDC, Synthesis, Constraints Development. Assist and mentor the team in day-to-day activities and grow the capabilities of the RTL Design team for future assignments. Review various results and reports to provide continuous feedback to the team and improve the quality of deliverables. Report status to management and provide suggestions to resolve any issues that may impact execution. Understand the complexity and requirements of RTL Quality Signoff and propose resource requirements to complete the activities. Work with peers to improve methodology and improve execution efficiency. Collaborate with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tools. Train the team in design concepts and root-cause analysis. The Impact You Will Have: Drive the successful delivery of SoC Subsystems by leading a skilled team of RTL Design Engineers. Enhance the quality and efficiency of RTL Design and Signoff processes through continuous feedback and methodology improvements. Ensure customer satisfaction by understanding their needs and delivering high-quality solutions. Contribute to the growth and development of the RTL Design team, expanding their capabilities for future projects. Support Synopsys reputation as a leader in chip design and verification through successful project execution. Foster collaboration and innovation within the team and across different Synopsys departments. What You ll Need: B.E/B. Tech/M.E/M. Tech in electronics with a minimum of 12+ years experience in SoC RTL Design. Technical expertise in various aspects of RTL Design and Signoff: LINT, CDC, RDC. Technical expertise on setting up flows and methodologies for quick deployment of RTL Signoff tools. Technical expertise in debugging and diagnosing violations and errors. Technical expertise in developing timing constraints and running preliminary synthesis for timing constraints check and area estimation. Ability to lead and manage a team to perform RTL Signoff on complex SoC/Subsystem. Experience with planning and managing various activities related to RTL Signoff and Design. Strong understanding of design concepts, ASIC flows, and stakeholders. Good communication skills. Who You Are: A proactive leader with excellent managerial skills. A team player who can mentor and guide engineers. An effective communicator who can interact with customers and stakeholders. A problem-solver with a keen eye for detail. An innovator who continuously seeks to improve processes.