Collaborate with cross-functional teams to drive product success. Develop and execute product engineering strategies. Serve as the technical interface between teams. Engage with sales and pre-sales teams to align product goals. Build and manage time plans and schedules for product development. Ensure seamless communication and coordination across different levels of the organization. The Impact You Will Have: Drive innovation in VLSI product engineering, influencing the development of cutting-edge technology. Enhance product quality and performance through strategic engineering initiatives. Foster collaboration and knowledge sharing across cross-functional teams. Contribute to the successful execution of complex projects, meeting organizational goals. Enhance customer satisfaction by delivering high-quality, reliable products. Support the growth and development of the Synopsys product portfolio. What You ll Need: Minimum 8 years of experience in VLSI product engineering. Exposure to analog and digital SOC design flows and methodologies. Experience in RTL Development, RTL Verification, and RTL to GDS flow. Proven track record of working on different technology nodes and driving product innovation. Strong customer-centric approach with the ability to manage multiple projects. Who You Are: Excellent communicator with strong written and verbal skills. Adept at interfacing with various organizational levels. Proficient in database management and ensuring data cleanliness. Knowledgeable about industry trends and emerging technologies in VLSI. Motivated and experienced professional looking for a new challenge

Lead the architecture and development of analog/mixed-signal blocks for PCIe 6 and PCIe 7 PHY designs. Ensure designs meet PCIe protocol standards, optimizing for performance, power, and area targets. Oversee the porting of PHY designs to different technology nodes, maintaining signal integrity and performance. Collaborate with cross-functional teams to integrate analog circuits into larger SerDes PHY systems. Develop and implement verification strategies for high-speed analog/mixed-signal circuits using advanced simulation tools. Supervise physical layout to minimize parasitics, device stress, and process variation impacts. Review simulation and measurement data for design validation and compliance with PCIe standards. Provide technical leadership and mentorship to junior engineers in analog/mixed-signal design best practices. Document design features, specifications, test plans, and methodologies for future reference. Collaborate with the characterization team to validate the electrical performance of circuits in silicon. The Impact You Will Have:Drive the development of next-generation PCIe 6 and PCIe 7 PHY designs, contributing to the advancement of high-speed interface technology. Ensure that Synopsys analog/mixed-signal circuits meet stringent industry standards, enhancing the companys reputation for excellence. Facilitate the seamless integration of analog circuits into complex SerDes PHY systems, improving overall system performance. Mentor and develop junior engineers, fostering a culture of continuous learning and innovation within the team. Contribute to the successful porting of PHY designs across different technology nodes, ensuring versatility and adaptability. Enhance the companys design verification processes, leading to more robust and reliable high-speed analog/mixed-signal circuits. What You ll Need:PhD with 5+ years, or MTech/MS with 10+ years of experience in analog/mixed-signal circuit design, with a focus on high-speed interfaces such as PCIe 6/7 or SerDes PHY designs. Extensive experience in transistor-level design of high-speed analog building blocks, such as LDOs, Bandgap references, ADC/DAC, PLLs, DLLs. Proven silicon experience in developing PHY circuits that meet strict PCIe standards. Expertise in high-speed SerDes AFE (Analog Front-End) development, including CTLE and CDR design. Experience designing high-speed SerDes transmitters, with in-depth knowledge of equalization techniques (e.g., DFE, FIR filters, TX pre-emphasis). Strong background in jitter budgeting analysis, including understanding the sources of jitter and strategies for minimizing its impact on signal integrity. Extensive experience with the porting of PHY designs across different technology nodes. Strong expertise in CMOS technologies, including finFET and SOI processes. In-depth understanding of the PCIe protocol, signal integrity requirements, jitter performance, and high-speed clocking. Proven ability to supervise layout design to minimize the effects of parasitics, process variations, and electromigration. Demonstrated ability to lead and mentor design teams, working across departments to ensure successful project outcomes

Designing and verifying digital and mixed-signal circuits for NRZ and PAM-based SerDes products. Collaborating with a team of experienced engineers to deliver high-performance mixed-signal designs. Developing and executing structured firmware development, verification, and documentation processes. Performing functional and performance tests on prototype test-chips. Communicating effectively with different design groups and customer support teams. Balancing good design quality while meeting tight deadlines. The Impact You Will Have:Contributing to the development of cutting-edge SerDes products that drive the innovations of tomorrow. Ensuring high-performance and reliable mixed-signal designs that meet unique performance, power, and size requirements. Accelerating the integration of more capabilities into an SoC, helping customers bring differentiated products to market quickly with reduced risk. Enhancing Synopsys reputation as a leader in chip design and software security. Driving the success of our Silicon IP business by delivering high-quality mixed-signal designs. Playing a key role in the continuous technological innovation at Synopsys. What You ll Need:BSEE or MSEE plus a minimum of 5 years industry experience in Silicon Bring up and Functional Validation. Experience with structured firmware development, verification, and documentation processes. Proficiency in digital logic design, simulation, and debug using Verilog and VCS. Demonstrated experience executing projects from start to completion. Good communication skills for interacting between different design groups and customer support teams

Key Qualifications Proven desire to learn and explore new state of the art technologies Demonstrate good written and spoken English communication skills Demonstrate good review and problem-solving skills Knowledgeable with Verilog, VHDL and/or SystemVerilog Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus Understanding of verification methodology such as UVM . Good organization and communication skills Be a solution provider. 8+ years of relevant experience

What You ll Need: Fluency in C/C++ with a strong background in data structures and algorithms. Experience with UPF and familiarity with Tcl and Python-based development on Unix (preferred). Knowledge of Verilog, SystemVerilog, and VHDL HDL (preferred). Experience with production code development on Unix/Linux platforms. Ability to develop new architectures and demonstrate strong leadership skills.

What You ll Need: BSEE in Electrical Engineering with 10+ years of relevant experience or MSEE with 8+ years of relevant experience. Experience in developing System Verilog based test environments and implementing test plans. Strong HVL coding skills and hands-on experience with industry-standard simulators and waveform-based debugging tools. Familiarity with verification methodologies such as VMM, OVM, or UVM. Knowledge of protocols such as AMBA, SD/eMMC, MIPI-I3C/UFS/Unipro, Ethernet, DDR, PCIe, and USB.

Collaborating with cross-functional teams to define project requirements, scope, and objectives. Developing detailed project plans, including timelines, resource allocation, and risk management strategies. Monitoring project progress and performance, identifying potential issues, and implementing corrective actions as needed. Communicating project status, updates, and milestones to stakeholders, ensuring transparency and alignment. Representing R&D on customer relationships, tracking execution to plan, aligning with senior leadership of team on mitigation and escalation management Mentoring and guiding team members, fostering a collaborative and innovative work environment. The Impact You Will Have: Driving the successful execution of engineering projects, contributing to Synopsys reputation for excellence and innovation. Enhancing the efficiency and effectiveness of project management processes, leading to improved project outcomes. Facilitating cross-functional collaboration, ensuring that all teams are working towards common goals. Providing leadership and mentorship to team members, fostering their professional growth and development. Ensuring that projects are delivered on time, within scope, and within budget, contributing to the overall success of the organization. Identifying opportunities for process improvements and implementing best practices to enhance project delivery.

SRE lead with capability to execute SRE lifecycle and automation process. Discover, design, and implement changes to existing IT infrastructure with a focus on improved reliability, performance, and standardization. Collaborate with Engineering and business units to translate customer, business, and technical requirements into SRE architectural designs and enhancements. Develop and analyze various business and technical scenarios to drive the highest levels of executive decision-making around infrastructure resources. Drive consensus and decisions with stakeholders. Troubleshoot production issues providing root cause analysis and designing solutions to prevent future occurrences. Build automated, scalable, and rigorous solutions to infrastructure problems by leveraging or developing state-of-the-art automation, mathematical optimization, and/or AI models. Monitor services and create intelligent alarming for quicker incident detection and resolution. Identify opportunities to invent and simplify processes, identifying business risks and implementing resolutions and scalable mechanisms. Ensure efficient resource utilization and continuously improve processes leveraging automation and internal tools resulting in enhanced service delivery, maturity, and scalability. Mentor and coach other SRE team members. The Impact You Will Have: Enhance the reliability and performance of Synopsys IT infrastructure. Standardize and automate processes to increase operational efficiency. Translate complex requirements into actionable SRE designs and solutions. Provide critical insights and drive decision-making for infrastructure improvements. Prevent future production issues through meticulous root cause analysis and proactive solutions. Contribute to the scalability and robustness of our infrastructure through innovative solutions. Enhance incident detection and resolution times, ensuring minimal disruption. Streamline processes to mitigate business risks and improve scalability. Optimize resource utilization, ensuring cost-effective and efficient operations. Develop the next generation of SRE talent through mentorship and coaching. What You'll Need: Extensive experience with a wide range of infrastructure technologies, such as Linux, Windows, High-performance computing, storage platforms, networking, cloud computing, cloud services (IaaS, PaaS, SaaS), virtualization, OpenStack, containerization, and orchestration technologies (e.g., Docker, Kubernetes). Expertise in HPC components like NFS/Shared File systems and Grid Schedulers (IBM spectrum LSF / Univa Grid / SLURM). Deep understanding of IT infrastructure-related services and their dependencies required to troubleshoot issues and define mitigations. Strong command and understanding of statistical concepts/models/analysis and how they relate to product reliability & life cycle analysis. Experience developing quantitative and qualitative analysis and metrics to solve business problems. Experience with developing service level indicators and objectives, instrumenting software, and building alerts. Hands-on experience with one or more of Java/Python/Go/AngularJS/NodeJS languages. Implementation experience in infra-automation tools and frameworks like GitHub, Maven/Gradle, Jenkins, Terraform (IaC), Ansible, Shell scripting.

Designing and implementing SOC solutions for various applications, ensuring high performance and reliability. Collaborating with cross-functional teams to define and develop SOC architecture and specifications. Conducting verification and validation of SOC designs to ensure compliance with industry standards and customer requirements. Optimizing SOC designs for power, performance, and area (PPA) to meet project objectives. Debugging and resolving issues in SOC designs, utilizing advanced tools and methodologies. Providing technical guidance and mentorship to junior engineers, fostering a culture of continuous improvement and innovation. Job Description and Requirements The role is for RTL Design and Signoff of IP/Subsystem/SoC Design in the System Solutions Group (SSG). At SSG, we are a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, and methodology to enable our customers to complete their most challenging SoC Design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies. As part of this role, you can expect to develop and deliver your expertise in RTL Signoff and RTL Design Techniques while working on activities such as Lint/CDC/RDC Checks, Timing Constraints Development, Preliminary Synthesis, Formality, and RTL Design. The role will expose you to various innovative technologies deployed for RTL Quality Signoff for Semiconductors. Responsibilities Perform RTL Quality Signoff Checks such as LINT, CDC, RDC. Understand the design/architecture and develop timing constraints for synthesis and timing. Run preliminary synthesis to ensure that the design can be synthesized as intended. Run formality to ensure equivalence of RTL and gates. Integrate IPs in SoCs/Subsystems and create RTL design as per need of the customer.

The candidate will be part of the Synopsys CXL IP Design verification R&D team at Synopsys. You will own UVM based verification environment, which handles multiple features of IP, test plan creation, test case writing, random constraint creation, coverage closure, SVA and Release. As part of the work, you will closely work with lead and be part of a global team of experienced Engineers. Technical Expertise Needed: BS or MS degree in Computer Science, Electrical or Electronics Engineering, or Related Field with 8+ years of experience in the following areas: Own UVM based testbench environment and developed UVM testbench architecture, Testplan and SVA for an IP/SoC. Knowledge of one or more of protocols/standards: PCIe, CXL, UCIe, AMBA (AXI,APB,AHB) etc Good knowledge of System Verilog. Hands-on experience with coverage closure and writing SVA for IP/SOC. Good simulation debugging skills. Experience with Perforce or similar revision control environment. Experience with Python/TCL or any scripting knowledge is an added advantage. Job Responsibilities include - Understand Standard Specifications, create testplan for the product and create UVM based testbench architecture. Propose and enhance the UVM architecture with unique idea for verification. Be single point of contact with hands-on experience on all verification tasks - Testbench Creation - Testplan creation - Coverage closure - SVA - Release Perform peer review of testbench code for continuous quality. Own simulation debugs using DVE/Verdi, interact with Design Team and aid in debug and Verification closure. Periodically publish technical papers and/or file patents on the feature updates/innovation carried out. The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide. In addition, the candidate should have excellent oratory and written communication skills in English, should be a team player and possess good problem-solving skills and show high levels of initiative.

What You ll Be Doing:Designing, coding, and testing software components with proficiency in C++ programming. Creating and maintaining Makefiles, BOM files, and build systems to streamline the software build and deployment process. Utilizing scripting languages such as Python, Shell, and Perl for automation, testing, and system-level tasks. Applying ML/AI technologies to enhance operations projects and develop sophisticated algorithms. Collaborating with cross-functional teams throughout the software development lifecycle, from concept to deployment. Troubleshooting and resolving software-related issues in a Linux environment. The Impact You Will Have:Contributing to the development and enhancement of cutting-edge software applications. Improving the efficiency and reliability of software build and deployment processes. Automating repetitive tasks and optimizing system-level operations. Enhancing the capabilities of operations projects with advanced ML/AI technologies. Ensuring seamless collaboration and communication within cross-functional teams. Resolving complex software issues and contributing to a robust and reliable software environment. What You ll Need:Bachelors or Masters degree in Computer Science, Software Engineering, or a related field. 2-6 years of relevant experience in software development and R&D projects. Strong proficiency in C++ programming and software design. Experience with data structures and algorithms. Knowledge of version control systems (Perforce, Git, SVN). Familiarity with Makefiles and build systems. Proficiency in scripting languages like Python, Shell, and Perl. ML/AI experience is essential. Solid understanding of Linux environments.

You're an experienced and highly motivated individual with a passion for technology and innovation. You have a strong technical background in RTL, Physical Design, and post-silicon test and testability development. Your expertise in debugging and developing Process, Voltage, Temperature, Current, and Droop sensors is unparalleled. You thrive in a dynamic environment and excel in communication, teamwork, and leadership. You're eager to learn and contribute to the development of state-of-the-art PVT IP sensors that are integral to the silicon lifecycle monitoring process. You possess a mindset geared towards meticulous IP debug and documentation, ensuring the highest standards of product development and performance. What You'll Be Doing: Serving as the single point of contact for post-silicon debug activities. Enabling Product Requirement Documents (PRDs). Working to enable IP as a product development platform. Handling hands-on post-silicon test setups. Collaborating on top-level physical design, board-level, and package-level designs. Developing post-silicon reports and conducting debug analysis. The Impact You Will Have: Driving the successful development and deployment of PVT IP sensors. Enhancing the reliability and performance of Synopsys silicon lifecycle monitoring solutions. Ensuring high-quality product development through meticulous testing and debugging. Contributing to continuous innovation in chip design and software security. Supporting Synopsys leadership in the market for PVT IP developments. Empowering the creation of high-performance silicon chips used in various advanced technologies. What You'll Need: Hands-on experience in post-silicon test setups. Sound knowledge of Digital/AMS chip design and post-silicon debug. BS or MS degree in Electrical Engineering with 3+ years of experience. Understanding of top-level physical design, board-level, and package-level designs. Expertise in RTL development and physical design.

Requirements: Bachelors/masters with good academic record. 5+ years experience in developing HVL based verification environments, preferably using System Verilog. Exposure to coverage driven verification. Experience in verification methodologies like UVM/OVM. Exposure to complex SV test benches involving multiple protocols and VIPs. Experience in VIP development is highly desirable. Should have a work exposure on any of the industry standard protocols like Jedec UFS, MIPI Unipro, MIPI MPHY, PCIe, USB, Ethernet, etc. Demonstrates good analysis and problem-solving skills. Have a strong passion for work and driving things to closure. Leadership qualities to motivate and align team members towards business goals and priorities. As a motivator/leader of the R&D team in Synopsys, you will be responsible for Development and enhancements of features, flows and solutions Quality execution of VIP development, taking responsibility for designing, developing, debugging, creation of reliable plans and effort estimates for your projects. Focus on innovation to ensure continuous product enhancements

What You ll Need: Degree or masters in electronics, science, hardware, computing, software, physics, mathematics, or engineering discipline. 3-7 years of technical writing experience in the software or hardware industry. Excellent problem-solving skills and strong logical reasoning. Experience with authoring tools such as FrameMaker. Excellent English writing and speaking skills.

You will get an opportunity to work on latest Synopsys implementation technologies (Machine Learning, Physical Synthesis , Multi-Source CTS, etc.) to solve complex PPA challenges faced by Synopsys customers. Working on benchmarks to displace competition implementation solutions. Working on developing and debugging RTL-GDS implementation methodologies and flows. Providing technical solutions by identifying the design and/or EDA tool issues and provide an appropriate solution for customers. Effectively translate the findings into requirements for R&D to improve both tool behavior with enhancements as adaptive long-term solutions. Involved in deployment of new technologies on latest EDAversions and enable customers to migrate to newer versions achieving best PPA. Coming up with a proactive understanding of customers pain point and coming up with innovative solutions to address the same. Closely interacting with Synopsys R&D team and product development team to develop future technologies. This role requires you to act as customers advocate while talking to inhouse R&D and be a product brand ambassador while engaging with customers. The candidate must have good exposure to methodology changes to achieve targeted PPA metrics for complex designs. At least 2 years of experience in Physical Implementation RTL-GDS. Experience in autonomously debugging and resolving synth & PnR implementation challenges. Proficiency in Synopsys implementation tools is an advantage. The individual must be self-motivated and dedicated with strong debugging skills. Requires proficiency in scripting (tcl / unix / perl). Excellent communication skills including the ability to interface with customers and business unit personnel are essential.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: An experienced and passionate Analog Design Engineer with 1-3 years of experience in the field You have a strong background in CMOS processes and deep submicron process technologies You understand the intricacies of CMOS circuit design and layout methodology, and you have a basic understanding of analog/mixed signal circuitry Familiarity with ESD concepts is a plus You are knowledgeable about ASIC design flow and JEDEC requirements for DDR interfaces and standards You excel at executing circuit design tasks with a focus on quality and efficiency Your communication skills are excellent, enabling you to interact effectively with internal development teams, What Youll Be Doing: Designing DDR/HBM Memory Interface I/O circuits and layouts, including GPIO and special I/Os, Collaborating with the DDR/HBM PHY team, package engineers, and system engineers to meet design specifications, Ensuring adherence to best practices in circuit design and layout methodology, Conducting thorough design reviews and contributing to the continuous improvement of design processes, Staying updated with the latest advancements in analog design technologies and methodologies, Documenting design processes and providing support for design validation and testing, The Impact You Will Have: Enhancing the performance and reliability of our analog and mixed-signal circuits, Contributing to the development of high-performance DDR/HBM Memory Interfaces, Supporting the overall success of our chip design and IP integration projects, Driving innovation in analog design methodologies and processes, Ensuring our products meet the highest standards of quality and efficiency, Helping Synopsys maintain its leadership position in the semiconductor industry, What Youll Need: Bachelor's or Master's degree in Electronics or Electrical Engineering, 1-3 years of experience in CMOS processes and deep submicron technologies, Proficiency in CMOS circuit design and layout methodology, Basic understanding of analog/mixed signal circuitry, Familiarity with ASIC design flow and JEDEC requirements for DDR interfaces, Who You Are: A detail-oriented engineer with a passion for analog design, An effective communicator who collaborates well with cross-functional teams, A problem-solver who can analyze and address design challenges efficiently, A continuous learner who stays updated with industry trends and advancements, A team player who contributes to the overall success of the project, The Team Youll Be A Part Of: You'll join a dynamic and innovative team of engineers focused on advancing our analog design capabilities Our team is dedicated to pushing the boundaries of technology and delivering cutting-edge solutions for the semiconductor industry We value collaboration, creativity, and a commitment to excellence in everything we do, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

What You ll Be Doing: Developing and maintaining documentation for EDA products used by chip designers and scientists. Planning, organizing, and creating user guides, reference material, and release notes for design engineering audiences. Researching and organizing initial source material into high-quality drafts, including product specifications,training materials, and engineering input. Collaborating with Applications and R&D engineers to solicit feedback and reviews. Implementing good standard writing practices to develop clear and concise technical content. Ensuring documentation is up-to-date with the latest product releases and features. The Impact You Will Have: Enhancing the usability and adoption of Synopsys products through clear and comprehensivedocumentation. Supporting the success of chip designers and scientists by providing them with the information they need to effectively use Synopsys tools. Improving customer satisfaction by addressing their requirements through well-crafteddocumentation. Contributing to the overall quality and reliability of Synopsys products by ensuring accurate and detaileddocumentation. Facilitating better communication and collaboration between engineering teams and end-users. Helping to drive continuous improvement in documentation processes and standards. What You ll Need: Bachelor s or Master s degree in Engineering or Science. 5 to 12 years of technical writing experience in a software product development company. Good knowledge of technical writing standards and processes. Ability to grasp new technology quickly. Excellent written and verbal communication skills. Experience with DITA and XML authoring tools such as Oxygen XML Author. Working knowledge of UNIX or Linux. Experience with electronic design automation (EDA) tools.

Designing software to support large-scale geometric data analysis and high-performance computing for OPC solutions. Optimizing infrastructure for distributed computing, ensuring seamless GPU integration. Collaborating with development teams to ensure efficient data handling and computational resource allocation. Debugging and troubleshooting infrastructure issues related to production line integration. Maintaining and troubleshooting the tool to meet performance and scalability requirements. Regularly contributing to the cutting-edge of semiconductor development by enhancing software performance and scalability. The Impact You Will Have: Advancing the development of high-performance silicon chips and software content. Enabling leading IC manufacturing through efficient software solutions. Contributing to the optimization of infrastructure for distributed computing. Ensuring seamless integration and operation of infrastructure components. Improving software performance and scalability for large-scale data analysis. Enhancing the overall efficiency and effectiveness of semiconductor development processes. What You ll Need: M.S. or Ph.D. in Computer Science, Engineering, or the Physical Sciences. 6+ years of experience in software development, with a focus on computational geometry and distributed processing. Expertise in C++, Python, and distributed computing environments. Experience in debugging and troubleshooting production-related issues. Strong communication and collaboration skills to work as part of a global team. Who You Are: A proactive problem solver with a passion for innovation. Detail-oriented with a focus on optimizing performance and scalability. An effective communicator with the ability to collaborate across teams. A self-motivated individual who can work independently with limited supervision. A sophisticated professional with advanced knowledge and wide-ranging experience.

Academic Qualification/Skills required: B.E / M.E. in Electronic & Communication / Computer Science Engineering High performance individual to work on Synopsys next generation emulation solutions for PCIe, USB, Ethernet protocols Good knowledge of one of peripheral protocols primarily PCIe, USB, Ethernet Knowledge of System Level verification and validation, and digital design concepts Knowledge of languages such as Verilog, System Verilog, C/C++, and scripting languages- Perl/TCL/Shell, Python Knowledge of emulation and prototyping domains an added advantage 6-8 Years of experience in protocols/design verification and validation, scripting, and automation Good communication skills and team player At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Developing Sign Off ECO optimization algorithms and heuristics. Debugging issues related to design loading and timing/power optimization. Striving for continuous improvements in QoR to achieve faster timing convergence with optimal power overhead. Collaborating with a team of engineers to develop technical solutions to complex problems. Communicating with product engineers to understand and define problem scope. Ensuring strict performance and quality requirements are met. The Impact You Will Have: Enhancing the performance and efficiency of PrimeClosure, the industrys first AI-driven signoff ECO solution. Contributing to the development of cutting-edge algorithms that optimize timing and power in chip design. Improving the overall quality and reliability of our products through rigorous debugging and testing. Driving innovation and continuous improvement in our engineering processes. Supporting customer success by resolving issues and implementing new features based on their feedback. Helping shape the future of AI-driven optimization in the semiconductor industry. What You ll Need: A degree in Computer Science or Electronics. 5+ years of experience in relevant field Strong analytical and problem-solving skills. Proficiency in C/C++ and Linux. Excellent communication and teamwork abilities. A passion for technology and innovation. Who You Are: A collaborative team player who thrives in a dynamic and innovative environment. A proactive and self-motivated individual with a strong attention to detail. An excellent communicator who can articulate complex ideas clearly and effectively. A creative thinker who is always looking for new ways to solve problems and improve processes. A dedicated professional committed to delivering high-quality work