Serving as the primary technical interface with customers, assisting them in evaluating, using, and applying TCAD tools. Providing technical support, troubleshooting, and resolving complex issues related to TCAD products. Managing new and existing customer relationships, ensuring high levels of customer satisfaction. Preparing and delivering technical training and presentations to customers and internal teams. Conducting beta testing, benchmarking, and onsite evaluations to support product development and customer needs. Collaborating with R&D to specify new features and drive continuous product improvement. The Impact You Will Have: Enhancing customer experience and satisfaction with Synopsys TCAD products. Driving the successful adoption and integration of TCAD tools in leading semiconductor companies. Contributing to the development and refinement of state-of-the-art TCAD tools. Strengthening Synopsys market position through exceptional technical support and customer engagement. Facilitating knowledge transfer and training to empower customers and internal teams. Playing a key role in the continuous innovation and advancement of semiconductor technology. What You ll Need: PhD in Electrical Engineering, Physics, or a related field. Strong background in semiconductor manufacturing technology and device physics. Proficiency in numerical methods and simulation tools. Excellent IT skills, particularly in Linux, Python, and TCL scripting. Minimum of three years of experience with TCAD simulation tools. Who You Are: A proactive and customer-oriented professional with excellent communication skills. Detail-oriented with strong problem-solving abilities. A collaborative team player who thrives in a dynamic environment. Adaptable and able to manage multiple priorities effectively. Passionate about technological innovation and continuous learning.

The successful candidate: - has solid engineering understanding of the underlying concepts of IC design,implementation flows and sign-off methodologies for deep submicron design. - has intimate knowledge of the full design cycle from RTL to GDSII, including development of timing constraints - has good scripting & programming skills (Perl, Tcl, Python etc); knowledge of CAD automation methods. - Can interface with the larger product team to understand design constraints, deliverable formats, customer requirements - Independent, timely decision maker and able to cope with interrupts - Knowledge of IP Subsystem implementation & FE flows are added advantages 8+ years of hands-on experience in ASIC physical implementation and EDA tools with recent contribution to project tape-outs.Must demonstrate knowledge of the Synopsys tools, flows and methodologies including Design Compiler, IC Compiler/2, Fusion Compiler, Primetime, Formality, Star-RCXT, Hercules/ICV and other industry tools.

You are a highly skilled engineer with a strong foundation in analog and mixed signal integrated circuit design. You bring both theoretical knowledge and practical experience to the table, enabling you to contribute effectively to our fast-growing R&D team. With a background in transistor-level circuit design, CMOS fundamentals, and high-speed logic paths, you excel in a dynamic environment. Your expertise in timing analysis, characterization, and modeling sets you apart. You thrive in cross-functional teams, collaborating with diverse professionals from various backgrounds to achieve common goals. Your proficiency with IC design tools, along with your familiarity with scripting languages like TCL, Perl, C, Python, and MATLAB, makes you a valuable asset to our team. You are detail-oriented, possess excellent communication skills, and are accustomed to working in a globally diverse environment. What You ll Be Doing: Direct and guide the activities of a team of engineers characterizing timing, analyzing timing results, and generating timing models of high-speed SERDES IP. Develop and align timing flow and methodology to ensure efficiency and quality of the team s deliverables. Conduct design reviews and evaluate final results of timing views and reports. Present results of timing assessments or critical issue investigations and make recommendations for actions necessary to achieve desired results. Ensure the team follows processes for maximum design quality. Consult on the timing characteristics of the SerDes IP product and propose solutions for STA timing closure. The Impact You Will Have: Enhance the performance and reliability of high-speed analog integrated circuits through meticulous timing analysis and characterization. Contribute to the development of cutting-edge SERDES IP, driving advancements in high-speed data communication. Improve the efficiency and quality of deliverables through optimized timing flow and methodology. Ensure maximum design quality by adhering to established processes and best practices. Provide critical insights and recommendations to address timing issues and achieve desired results. Collaborate with cross-functional teams to deliver innovative solutions that meet the evolving needs of the semiconductor industry. What You ll Need: MSc in Electrical Engineering or related field with 2 years of experience in IC design. Familiarity with transistor-level circuit design and CMOS design fundamentals. In-depth knowledge of setup and hold timing analysis. Experience in timing characterization, modeling, simulation, and verification. Familiarity with custom digital design (i.e., high-speed logic paths). Experience with timing tools such as Primetime, NanoTime, or equivalent. Hands-on experience with the physical layout of high-speed circuits is a plus. Knowledge of SPICE simulators and simulation methods. Proficiency in scripting languages such as TCL, Perl, C, Python, MATLAB. Who You Are: Detail-oriented and capable of conducting thorough analyses. Strong communicator with excellent documentation skills. Collaborative team player comfortable in a cross-functional, globally diverse environment. Creative problem solver with the ability to think critically and propose effective solutions. Adaptable and able to work at all levels of an organization

What You ll Need: Good understanding of electronics basic concepts and applications. In-depth knowledge of logic gates, flip flops, latches, multiplexers, level shifters, and digital logics. Experience with CMOS design and layout concepts, especially in lower node technologies. Familiarity with ASIC design flow and layout automation. Proficiency in programming languages such as C, Python, Perl, and UNIX. Who You Are: Adept at innovative and out-of-the-box thinking. Systematic in your approach to problem-solving. Excellent written and verbal communication skills. Comfortable working with diverse teams globally. Capable of leading projects and making strategic decisions.

Design and implement Data Ingestion & Processing pipelines for our Sentaurus Calibration Workbench (SCW) - Format support, validation, DB with search/filters, AI/ML-driven analysis. Integrate core TCAD simulation engines with SCW - Optimize connectivity to reduce turnaround time (TAT), improve scalability, quality of results (QoR), and ease-of-use (EoU) Collaborate closely with the product application engineering (PAE) team to ensure functionality and quality requirements are met. Collaborate closely with the front-end team to ensure backend features are seamlessly integrated into the GUI for end-users. The Impact You Will Have: Drive advancements in TCAD calibration automation, leading to significant improvements in simulation efficiency and accuracy. Enhance the user experience by supporting integration of backend features into a user-friendly GUI, enabling seamless deployment of calibration workflows to customers. Support the creation of innovative solutions that address complex semiconductor design challenges, contributing to the success of our customers. Streamline the TCAD calibration process, reducing TAT and improving overall productivity for both internal teams and customers. Foster collaboration and knowledge sharing within the team, driving continuous improvement and innovation in SCW. What You ll Need: MS or PhD in Computer Science, Software Engineering, Electrical Engineering, or equivalent. 4+ years of hands-on experience in software development with solid programming skills in C++ and Python. Solid data analysis knowledge and skills. Familiarity and hands-on experience with ML applied to data analysis and optimization. Strong desire to learn and explore new technologies. English language working proficiency and communication skills allowing teamwork in an international environment. Willingness to work in a distributed international team.

Driving engineering efforts related to Continuous Integration and Delivery (CI/CD) and automated testing and deployment across all phases of the Software Development Life Cycle. Implementing frameworks and best practices for deploying automation via pipelines into on-premises, cloud environments (AWS, GCP, Azure), and containerized environments (Kubernetes, Docker Swarm). Building platforms and frameworks to create consistent, verifiable, and automatic management of applications and infrastructure in both on-premises and cloud infrastructure. Defining the development pipeline to ensure that software development flows match operational testing and deployment goals. Working within the Agile framework to identify, create, design, and integrate processes for repeatable, automated software delivery. Identifying and initiating the development of metrics and dashboards to monitor the adoption and maturity of DevOps practices. Advocating for innovation and automation, continuously seeking ways to improve CI/CD processes. Reviewing technical operations and providing mentoring and oversight to other DevOps team members in implementing recommended solutions for process automation and best practices. The Impact You Will Have: Enhancing the efficiency and effectiveness of our CI/CD pipelines to ensure high-quality software delivery. Enabling consistent and automated management of applications and infrastructure, improving reliability and scalability. Streamlining the software development lifecycle, ensuring alignment with operational testing and deployment goals. Driving the adoption and maturity of DevOps practices through the development of metrics and dashboards. Fostering a culture of innovation and automation within the engineering team. Mentoring and guiding other DevOps team members, enhancing their skills and knowledge. What You ll Need: Bachelors or Masters degree in Engineering streams such as Computer Science, EEE, ECE, IT, or equivalent. At least 5 years of overall software development/deployment/infra experience. Cloud and other architect-level industry certifications (AWS, GCP, Azure, Security, etc.). 3-5 years of DevOps experience in modern tech stack to support products in the cloud. 2+ years of scripting/automation experience with Bash, Python, Perl, and/or other scripting languages. Strong CI/CD experience with code build, source control, testing, continuous integration, and delivery using standard DevOps CI/CD tools (Jenkins, Git). 3+ years of experience with containerization, source control (Docker/Docker Hub/Helm), and container orchestration (Kubernetes, Docker Swarm). Familiarity with programming languages (C/C++/Java). Familiarity with build tools (Make, CMake, Maven, Gradle) and dependency management (Conan). Experience developing Ansible Playbooks/Jenkins automation for infrastructure automation. Proficiency in multiple DevOps-related tools and technologies (JIRA, Confluence, GitHub/Azure, Jenkins, Ansible, Prometheus, Grafana, ELK).

Here's the information about the PrimeTime role, formatted for clarity and impact: Driving increased usage of the Synopsys PrimeTime tool through both pre-sale and post-sale activities. Conducting competitive benchmarks and evaluations to demonstrate the superiority of our products. Articulating technical advantages to customer design teams and management. Providing customer training and tapeout support to ensure successful product implementation. Collaborating with users, R&D, marketing, and sales teams to enhance product features and usability. Engaging in advanced collaboration initiatives to drive continuous product improvements. The Impact You Will Have Increasing the adoption and integration of PrimeTime, leading to higher customer satisfaction and retention. Enhancing customer design processes through expert guidance and support. Contributing to the development of superior product features based on customer feedback and industry trends. Strengthening Synopsys market position through effective pre-sale evaluations and demonstrations. Facilitating successful tapeouts and design completions for customers using PrimeTime. Driving innovation within Synopsys by collaborating with multiple teams and stakeholders. What You'll Need BSEE with 5+ years of experience or MSEE with 3+ years of experience in related fields. Domain knowledge in Static Timing Analysis (STA) and expertise in timing closure and ECO flows . Experience with Synopsys STA tools , particularly PrimeTime. Understanding of timing corners, modes, process variations, and signal integrity issues. Strong knowledge of TCL scripting and familiarity with synthesis, physical design, and extraction methodologies. Who You Are A proactive and detail-oriented professional with strong technical acumen. An effective communicator with excellent verbal and written communication skills. A collaborative team player who thrives in customer-facing roles. An innovative thinker who is always looking for ways to improve processes and products. A dedicated individual with a strong sense of ownership and responsibility.

A Hardware-Assisted Verification Expert with deep knowledge of IP interfaces such as PCIe and DDR, and experience with Zebu, HAPS, and EP platforms. You have a proven track record in IP verification and methodology ownership focused on emulation and verification. You thrive in a matrixed, international, and team-oriented environment with multiple stakeholders. Your hands-on approach, collaborative mindset, and proactive attitude drive results. You are passionate about working closely with customer, RND, PV and Product Engineering to work on latest emulation technologies to deploy and enhance optimal solutions covering the entire ecosystem of Large SOCs, Controller and PHY, with a focus on emulation and acceleration. What You ll Be Doing: Bridging and closing gaps between the available or required Emulation hyper scaler Designs, IP and product validations of all its functions. Reporting metrics and driving improvements in Emulation PE and RND Using your expertise to drive requirements for the Emulation and ensure its correct usage and deployment in verification strategies for customers. Staying ahead of evolving standards, understanding future changes, specification errata, and driving this understanding into both the Emulation IP and Design IP teams. The Impact You Will Have: Enhancing cross-functional collaboration to improve product quality and end customer satisfaction. Changing the mindset in the way we use Emulation IP in validating digital designs and architectures. Driving innovation in defining requirements for product development, in the context of Emulation. Evolving and integrating best-in-class methodologies within the organization. Standardizing and optimizing workflows to increase efficiency and compliance. What You'll Need: 8+ years of relevant experience. Results-driven mindset. Exposure to large design emulation compiles along with advanced protocols like PCIe and DDR interfaces. Experience with Zebu in the context of technology and SW validation. Proven track record in product deployment, specifically emulation. Experience in cross-functional collaborations. Excellent communication skills and a beacon for change. Adaptability and comfort in a matrixed, international environment.

Responsible for Analog design for MSIPs from architecture to production silicon Will set up and manage the team of Analog/Mixed Signal design experts Work out innovative design techniques to overcome challenges Team designs of bandgap, temperature sensors, Signa Delta ADCs , DAC, Voltage monitoring Ips, PLL Ensure right talent is identifies , managed , groomed and enable a stellar team performance Works together with global cross functional team for team s success Qualifications BS or MS degree in Electrical Engineering/Computer Science/Computer Engineering. 10 - 15 years of experience in the fields of Analog/Mixed Signal design for leading edge technologies Innovation mindset with system modelling, architecture and best design practices Ability to lead a large team that will cover different R&D project for AMS IP development . Strong knowledge about custom SOC flow desirable. Understanding of Analog, digital flow and post silicon test/characterization is a desirable skill High in drive and bringing positive energy leading towards a mission Strong personal value system Preferred Skills High drive and people leadership skill Demonstrated experience with Analog/Mixed Signal Design and IP/Product ownership with Analog and Digital subsystems Thorough knowledge of AMS design flow with digital top SOC integration methodology Closely work with Analog Design and layout team by reviewing and guiding for best-in-class performance People management expertise, ability to bring good people and lead them from front

Defining and developing ASIC RTL verification at both chip and block levels. Creating and executing verification plans for complex digital designs, particularly focusing on PCIe/CXL protocols. Collaborating with cross-functional teams to ensure seamless integration and functionality of designs. Utilizing advanced verification methodologies and tools to achieve high-quality results. Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement. Communicating with internal and external stakeholders to align on project goals and deliverables. The Impact You Will Have: Enhancing the reliability and performance of Synopsys digital verification processes. Improving time-to-market for robust Synopsys Interface IP controller through efficient verification methodologies. Mentoring and nurturing a highly skilled verification team, elevating overall project quality. Influencing strategic decisions that shape the future of Synopsys capabilities. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements. What You'll Need: Extensive experience in ASIC RTL verification. In-depth knowledge of PCIe, CXL , UCIe and similar IO protocols. Proficiency in advanced digital design verification tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams. Experience of 18+ years in relevant domain.

An experienced and passionate Applications Engineer, ready to join our dynamic team. You thrive in fast-paced environments and are driven by the opportunity to work with high-end customers in the Mobile Industry Processor Interface (MIPI ) domain. With your strong technical background in ASIC design, you are adept at providing top-tier technical support and guidance. Your excellent communication skills enable you to effectively interact with customers and internal teams alike. You are not just looking for a job, but a place where you can make a significant impact and grow your career. What You ll Be Doing: Providing technical support to field engineers and customers utilizing Synopsys MIPI UFS Intellectual Property (IP) Partnering with high-tech customers through the full cycle of ASIC design, from installation and training to RTL design and production testing Conducting reviews on customers major SoC design milestones Authoring application notes and white papers to promote the IPs ease of use and address specific challenges Providing feedback to internal teams for continuous product improvements based on customer feedback Ensuring successful integration of Synopsys MIPI IP solutions into customers SoCs The Impact You Will Have: Enhancing customer satisfaction by providing expert support and ensuring seamless integration of Synopsys IP Driving innovation by collaborating with customers on cutting-edge SoC designs Contributing to the development of industry-leading IP solutions through continuous feedback and improvement processes Expanding Synopsys market presence in the MIPI domain through successful customer engagements Promoting the adoption of Synopsys IP by authoring impactful documentation and white papers Supporting the growth of Synopsys IP portfolio by identifying and addressing customer needs What You ll Need: Bachelors degree with 5+ years or Masters degree with 2+ years of relevant experience in the ASIC design process Proficiency in Verilog HDL, synthesis, simulation, and verification Knowledge of Place and Route, Design Reuse, Physical Design, or Analog Design is a plus Familiarity with MIPI UFS/UniPro protocols, high-speed SERDES, or parallel interfaces is advantageous Experience with Synopsys tool suites is a plus Strong verbal and written communication skills in English

Deploying Synopsys DFT technologies on key customers designs and successfully executing the project. Acting as the focal point of contact and managing all external and internal communications across cross-functional teams. Planning and directing project schedules, identifying and escalating issues, and driving problems to resolution. Identifying and managing risks, ensuring the completion of projects on schedule and with high quality. Organizing interdepartmental activities and ensuring clear and concise communication. Working closely with internal teams (Applications Engineering, R&D) to meet customer requirements and achieve goals and targets. The Impact You Will Have: Ensure successful deployment of Synopsys DFT technologies on customer designs. Facilitate effective communication and coordination between cross-functional teams. Drive projects to completion, meeting deadlines and maintaining high standards of quality. Identify and mitigate risks to ensure project success. Contribute to the overall success of Synopsys by delivering high-quality solutions that meet customer needs. Enhance customer satisfaction and build strong, long-lasting relationships with key customers. What You'll Need: Solid background and proven track record in the implementation of DFT technologies. Experience in deploying Scan Compression, On-chip DFT Fabric, ATPG, Diagnosis, MemoryBIST, LogicBIST, and Boundary Scan. Proficiency in project management and the ability to manage multiple projects simultaneously. Exceptional verbal/written communication, leadership, interpersonal, and teamwork skills. Good working knowledge of PowerPoint, Excel, and Word.

This position typically requires at least 2 to 3 years of related IP design or customer experience, but we may also consider candidates with less experience with the right academic background. ASIC design experience with proven design background. Experience in one or multiple steps on IP design or integration flow of ASIC / SoC design (such as simulation/verification, RTL synthesis, floor planning, physical design, timing closure, etc.) and silicon bring-up/characterization in a system environment. Domain knowledge of at least one of the following protocols: PCI Express SERDES Serial ATA Good RTL and Gate Level simulation Debug skills Familiarity with Front end implementation like Synthesis, Static Timing Analysis, Logical Equivalence Check Preferred Experience Technical knowledge with any Interface IP such as PCIe, USB, SATA, MIPI, HBM DDR, LPDDR Protocols, Specification, Design, and Implementation flows with Design Compiler, Fusion Compiler and PrimeTrime. Excellent organization skills, excellent communication skills and ability to interact with customers Proven track record in meeting tight schedules and handling multiple projects concurrently

Working closely with customers to understand their requirements in verifying custom design IP. Tailoring solutions to address challenging verification scenarios for custom designs. Collaborating with the product team to define, test, and deploy new features. Providing technical support and expertise on Synopsys ESP equivalence check product. Conducting product demonstrations and training sessions for customers and partners. Developing and maintaining technical documentation and application notes. The Impact You Will Have: Enhancing customer satisfaction through effective technical support and custom solutions. Driving the adoption and integration of Synopsys ESP equivalence check product. Contributing to the continuous innovation and development of new product features. Ensuring the highest quality of custom designs by catching elusive corner case design inconsistencies. Building strong relationships with customers and fostering long-term collaborations. Expanding Synopsys market presence through successful customer engagements. What You'll Need: Bachelors or Masters degree in Engineering/Technology (Electronics/Electrical or related field). 1-2 years of experience in custom design verification. Understanding of circuits at SPICE netlist level and design description in Verilog/System Verilog. Knowledge of transistor-level design and simulation in MOSFET technology. Excellent written and oral English communication skills.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and initiative-taking individual with a strong technical background in Physical design, physical verification at IP/block/full chip level implementation/methodology. You thrive in collaborative environments and possess a passion for creating innovative technology. Your expertise lies in working with advanced Finfet and GAA process challenges, and you have a proactive analytical approach with a keen eye for detail. Your dedication to delivering high-quality results is complemented by excellent communication and people skills, allowing you to effectively collaborate with both internal teams and external customers. Driven by a desire to innovate, you are eager to contribute to the success of our cutting-edge technology products. What Youll Be Doing: * Conceptualizing, designing, and productizing state-of-the-art RTL to GDS implementation for SLM monitors realized through ASIC design flow. * Designing on-chip Process, Voltage, Temperature, glitch, and Droop monitors for monitoring silicon biometrics. * Physical verification, DRC, LVS, PERC, ERC, ESD, EM and Antenna cleaning. *Co-work with Place & Route team to resolve full chip/IP/block level layout integration issues to drive Physical Verification *Coordinates with internal IP owners on IP related issues. *Coordinates with Manufacturing Team on DRC related issues. * Creating new flows/methodologies and updating existing ones through collaboration with architects and circuit design engineering teams. The Impact You Will Have: * Accelerating the integration of next-generation intelligent in-chip sensors and analytics into technology products. * Optimizing performance, power, area, schedule, and yield of semiconductor lifecycle stages. * Enhancing the reliability and differentiation of products in the market with reduced risk. * Driving innovation in Physical verification and signoff design methodologies and tools. * Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions. * Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies. What You’ll Need: BS/B.Tech or MS/M.Tech degree in Electrical Engineering with 5+ years of relevant industry experience. Strong Physical verification and signoff experience. Experience in DRC, LVS, DFM, ANT, ERC, ESD, EM and PERC cleaning is mandatory. Proficiency with Digital design tool from any EDA vendor, preferably from Synopsys tools like FC & ICV Sound understanding of Physical design, Physical verification and signoff concepts. Work with various implementation team to drive full-chip/block level/IP level Physical Verification Sign-off closure in (DRC, LVS, ANT, ERC, ESD, PERC, EM) for tape-out. Experience with design methodologies like developing custom scripts and enhancing flows for better execution. Experience in scripting with TCL/PERL is required. Proven track record of successful physical verification closure & tape-outs in advanced nodes (14nm, 10nm, 7nm, 5nm,3nm,2nm etc...) Exposure to Floorplan & PnR flows and tools such as ICC2/FC/Innovus are added advantage. Good understanding of reliability physics including EM, ESD, crosstalk, shielding, latchup and deep sun-micron challenges. Who You Are: * Proactive and detail-oriented with excellent problem-solving skills. * Adept at working independently and providing physical verification and signoff solutions. * Excellent communicator and team player, capable of collaborating effectively with diverse teams. * Innovative thinker with a passion for technology and continuous improvement. * Committed to delivering high-quality results and achieving project goals.

- Hands-on development of layout for next-generation DDR/HBM/UCIe IPs. - Creating floorplans, routing, and performing physical verifications to meet quality standards. - Debugging and solving complex layout issues to ensure high-quality deliverables. - Collaborating with design engineers to optimize layout for performance, power, and area. - Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation. - Ensuring compliance with DRC, LVS, ERC, and antenna rules. The Impact You Will Have: - Contribute to the development of cutting-edge technologies that drive the Era of Smart Everything. - Enhance the performance and reliability of next-generation semiconductor IPs. - Accelerate the time-to-market for high-performance silicon chips. - Reduce risks associated with layout design by adhering to stringent verification requirements. - Foster a collaborative and innovative work environment. - Support Synopsys mission to lead in chip design and software security. What You ll Need: - BTech/MTech in Electrical Engineering or related field. - 2+ years of relevant experience in analog layout design. - Proficiency in developing quality layouts and performing physical verifications. - In-depth understanding of deep submicron effects and floorplan techniques. - Experience with CMOS, FinFET, and GAA process technologies at 7nm and below. - Knowledge of layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation.

You are a passionate and skilled Analog Layout Design Engineer with a keen eye for detail and a deep understanding of advanced semiconductor technologies. You thrive in dynamic environments and possess a strong problem-solving aptitude. With a profound expertise in developing high-quality layouts and physical verification techniques, you are ready to contribute to cutting-edge DDR/HBM/UCIe IP development. You excel in collaboration, fostering accountability and ownership within teams, and have excellent written, verbal communication, and interpersonal skills. Your commitment to diversity and inclusion aligns with Synopsys values, and you are eager to work in an environment that welcomes all perspectives. What You ll Be Doing: Hands-on development of layout for next-generation DDR/HBM/UCIe IPs. Solving complex problems and debugging issues effectively. Executing layout floor planning, routing, and physical verifications to meet stringent quality requirements. Ensuring compliance with DRC, LVS, ERC, and antenna rules. Applying deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies (7nm and below). Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation. The Impact You Will Have: Enhancing the performance and reliability of Synopsys DDR/HBM/UCIe IPs. Accelerating the integration of advanced capabilities into SoCs. Reducing risk and improving time-to-market for differentiated products. Driving innovation in semiconductor technology and design. Contributing to the success of Synopsys Silicon IP business. Fostering a collaborative and inclusive work environment. What You ll Need: BTech/MTech degree in a relevant field. 4+ years of experience in analog layout design. Proven track record in developing high-quality layouts and meeting verification timelines. Strong understanding of deep submicron effects and floorplan techniques. Exposure to layout matching, ESD, latch-up, EMIR, DFM, and LEF generation. Who You Are: Detail-oriented with excellent problem-solving skills. Collaborative and able to foster accountability and ownership. Strong written, verbal communication, and interpersonal skills. Committed to diversity and inclusion.

Category Engineering Hire Type Employee Job ID 10503 Remote Eligible No Date Posted 08/04/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and skilled Analog Layout Design Engineer with a keen eye for detail and a deep understanding of advanced semiconductor technologies. You thrive in dynamic environments and possess a strong problem-solving aptitude. With a profound expertise in developing high-quality layouts and physical verification techniques, you are ready to contribute to cutting-edge DDR/HBM/UCIe IP development. You excel in collaboration, fostering accountability and ownership within teams, and have excellent written, verbal communication, and interpersonal skills. Your commitment to diversity and inclusion aligns with Synopsys values, and you are eager to work in an environment that welcomes all perspectives. What You ll Be Doing: Hands-on development of layout for next-generation DDR/HBM/UCIe IPs. Solving complex problems and debugging issues effectively. Executing layout floorplanning, routing, and physical verifications to meet stringent quality requirements. Ensuring compliance with DRC, LVS, ERC, and antenna rules. Applying deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies (7nm and below). Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation. The Impact You Will Have: Enhancing the performance and reliability of Synopsys DDR/HBM/UCIe IPs. Accelerating the integration of advanced capabilities into SoCs. Reducing risk and improving time-to-market for differentiated products. Driving innovation in semiconductor technology and design. Contributing to the success of Synopsys Silicon IP business. Fostering a collaborative and inclusive work environment. What You ll Need: BTech/MTech degree in a relevant field. 4+ years of experience in analog layout design. Proven track record in developing high-quality layouts and meeting verification timelines. Strong understanding of deep submicron effects and floorplan techniques. Exposure to layout matching, ESD, latch-up, EMIR, DFM, and LEF generation. Who You Are: Detail-oriented with excellent problem-solving skills. Collaborative and able to foster accountability and ownership. Strong written, verbal communication, and interpersonal skills. Committed to diversity and inclusion

Bengaluru, Karnataka, India Category: Finance Hire Type: Employee Job ID 6504 Date posted 02/24/2025 R2R Accountant We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned accounting professional with over 10 years of proven experience in multi-country R2R (Record to Report) administration, particularly with a strong focus on Europe. You possess a deep understanding of Europe tax regulations and have a high degree of professionalism. You are adept at handling sensitive and confidential material and have excellent decision-making, problem-solving, and analytical skills. You have a degree or master’s degree from a recognized university and are proficient in both business needs and the technologies to implement them. Your interpersonal, written, and verbal communication skills are excellent, and you have a knack for delivering compelling presentations. You thrive in a collaborative environment and are always ready to support your peers to complete tasks efficiently. What You’ll Be Doing: Managing end-to-end R2R operations and related compliance activities for Europe entities. Performing month-end accruals and other closing deliverables for multiple Europe entities. Calculating Tax provision and CIT supporting. Setting up and monitoring recurring JVs in Blackline/SAP. Conducting cash forecasting and intercompany revenue forecasting. Reconciling open item GLs of the balance sheet using Blackline. Collaborating closely with departments such as AP, Treasury, Payroll, and Tax to minimize disputes. Understanding and ing Accounting Standards (US GAAP/IFRS). Preparing, posting, and reconciling intercompany invoices. Ensuring accuracy of financial report packs through R2R controls. Managing year-end statutory filings and closure activities. Organizing R2R function documentation (e.g., Desktop procedures, SOX Docs). Participating in ad-hoc projects to deliver process improvements and add value to the R2R organization. Contributing to tasks related to mergers and acquisitions. The Impact You Will Have: Ensuring timely and accurate financial reporting for multiple Europe entities. Maintaining compliance with Europe tax regulations and statutory requirements. Improving cash flow management through effective forecasting. Enhancing the accuracy and reliability of financial statements. Facilitating smooth audits through meticulous preparation and coordination. Driving process improvements and efficiency within the R2R function. Supporting organizational growth through participation in mergers and acquisitions. Fostering cross-departmental collaboration to resolve disputes and enhance operations. Contributing to a high-performance finance team through knowledge sharing and teamwork. What You’ll Need: 10+ years of experience in multi-country R2R administration, with a focus on Europe. A degree or master’s degree from a recognized university. Strong knowledge of Europe tax regulations. High degree of professionalism and ability to handle confidential material. Excellent decision-making, problem-solving, and analytical skills. Proficiency in accounting standards (US GAAP/IFRS). Experience with Blackline and SAP. Who You Are: Detail-oriented with a strong focus on accuracy. Effective communicator with excellent interpersonal skills. Team player who supports peers to achieve common goals. Proactive and able to work independently with minimal supervision. Adaptable and open to change, with a continuous improvement mindset. The Team You’ll Be A Part Of: As a member of the COE Finance team, you will be responsible for the daily operations of the Record to Report processes, ensuring that these processes are handled timely and efficiently. You will work closely with various departments such as AP, Treasury, Payroll, and Tax to ensure quality in reporting and compliance. The team is dedicated to continuous improvement and collaboration, striving to add value to the organization through innovative approaches and solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Bengaluru, Karnataka, India Category: Engineering Hire Type: Employee Job ID 9800 Date posted 02/28/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and innovative digital design engineer with extensive experience in ASIC design methodology and flows, with a particular emphasis on low power analysis and optimization. You thrive in dynamic environments and are passionate about pushing the boundaries of technology. With a strong background in both digital and physical design, you bring a deep understanding of the underlying concepts of digital design and architecture, physical implementation flows, and timing signoff. You have a proven track record of working with advanced nodes, particularly at 5nm and below, and are adept at developing timing constraints and UPF to meet stringent power, timing, and area targets. Your expertise in low-power design techniques at RTL and design implementation flow, coupled with your knowledge of SAIF-based analysis, positions you as a leader in the field. You are methodical and possess excellent software and scripting skills (Perl, Tcl, Python), with a solid understanding of CAD automation methods. You are an effective communicator, capable of articulating complex concepts at various levels of abstraction to peers, management, and customers. Autonomous and resilient, you handle interruptions with ease and maintain focus on delivering high-quality results. What You’ll Be Doing: Developing and driving digital design methodologies for low power analysis and optimization across IP development teams. Collaborating closely with design teams to implement state-of-the-art ASIC design methodologies. Working with EDA tools teams to understand and deploy the latest technologies. Creating and optimizing RTL designs to achieve the lowest power consumption. Conducting SAIF-based analysis and implementing best practices for low power design. Developing timing constraints and UPF to meet power, timing, and area targets. \The Impact You Will Have: Enhancing the power efficiency of high-performance silicon chips. Driving innovation in low power design methodologies. Influencing and shaping the methodologies used across multiple IP design teams. Contributing to the successful implementation of advanced node technologies. Ensuring the delivery of high-quality, low-power silicon IP products. Supporting the development of industry-leading mixed-signal products. What You’ll Need: MSEE or BSEE with 20+ years of digital design experience. 15+ years of digital and/or physical design experience, including hands-on contributions. Strong understanding of digital design and architecture, physical implementation flows, and timing signoff. Experience with low-power design techniques at RTL and design implementation flow. Proficiency with EDA tool flows and advanced node challenges at 5nm and below. Expertise in developing timing constraints and UPF for power, timing, and area optimization. Excellent software and scripting skills (Perl, Tcl, Python). Who You Are: You possess excellent organization and communication skills, with the ability to think and communicate at different levels of abstraction. You are methodical, autonomous, and capable of handling interruptions while maintaining focus. Your strong software and scripting skills complement your engineering expertise, allowing you to drive innovation and optimize design processes effectively. The Team You’ll Be A Part Of: You will be part of the new Digital Methodology Center of Excellence within Synopsys' world-class IP team. This team is dedicated to developing and implementing cutting-edge digital design methodologies that will be used across all IP development teams. You will collaborate with experienced digital and mixed-signal engineers, working on high-end mixed-signal products and contributing to every aspect of the digital design flows. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.