Required Qualifications: Bachelor with 4 years experience or MSEE (or PhD) with 2 years experience in Electrical Engineering, Computer Engineering, or similar technical field In-depth familiarity with transistor level circuit design - sound CMOS design fundamentals. Silicon-proven experience implementing circuits for the TX, RX and Clock paths within a SerDes Detailed design experience with several of the following SerDes sub-circuits: receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects. Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.). Experience with EDA tools for schematic entry, physical layout, and design verification. High proficiency with spice simulators including HSPICE, Finesim and XA Knowledgeable in Verilog-A and/or System-Verilog for analog behavioral modeling and simulation-control / data-capture. Plus Qualifications: Ability to provide automation for rapid and dynamic design needs is highly sought-after Experience with STA and cell characterization such as Nanotime, Primetime, SiliconSmart Experienced in STAR or similar extractor to debug extraction issues Extensive programming skills in languages such as Python, Perl, TCL and C/C++

Design and develop software for interface IP systems Perform Device level and System level, validation and debug, in post-silicon Software Development for new validation methodologies Customer interface to capture requirement and post release support Maximize software productivity and faster time to knowledge Qualifications: Qualification: B.Tech in ECE/CS or equivalent with 4+ year of relevant experience ECE background with experience is software is preferred Skills: Excellent programming and testing skills using C/C++ Experience with embedded or resource-constrained environments Development experience on Unix, Linux and Windows Ability to pick up new flow, learn on the Job MATLAB & PYTHON programming exposure is plus Excellent verbal and written communication skill

* Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc ) * Generate verification test plan, verification environment documentation and test environment usage documentation * Define, develop, and verify complex UVM verification environments * Evaluates and exercises various aspects of the development flow. May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modelling, and verification coverage metrics (functional coverage and code coverage) * Collaborate with architect, designers , VIP team to accomplish tasks. * Identify design problems, possible corrective actions and/or inconsistencies on documented functionality * Work with peers to improve methodologies and improve execution efficiency. * Adhere to quality standards and good test and verification practices. * Work as a lead, mentor junior engineers, and help them in debugging complex problems. * Able to Support Customer issues, by their reproduction and analysis. * Should be able multitask between different activities. Key Qualifications * Proven desire to learn and explore new state of the art technologies * Demonstrate good written and spoken English communication skills * Demonstrate good review and problem-solving skills * Knowledgeable with Verilog, VHDL and/or SystemVerilog * Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus * Understanding of verification methodology such as UVM . * Good organization and communication skills * Be a solution provider. * 8+ years of relevant experience

What You ll Be Doing: Designing and developing Test Automation Frameworks, approach, and methodologies for large enterprise projects. Creating, maintaining, and executing end-to-end test cases, test scripts, and test data. Defining test automation strategy, best practices, project structure, and review processes. Performing test infrastructure setup, upgrades, and migrations, including Tricentis Tosca. Managing users, projects, and test portfolios using Tosca Server and Tosca Commander. Integrating Tricentis Tosca with third-party tools. Conducting regular reviews and maintenance of the test portfolio to ensure adherence to best practices. Defining upgrade and maintenance approaches and performing necessary upgrades and migrations. Collaborating effectively with global cross-functional teams and stakeholders. Mentoring and guiding team members on test automation best practices. The Impact You Will Have: Enhancing the quality and reliability of software products through robust automation frameworks. Streamlining testing processes, leading to faster time-to-market for our solutions. Ensuring seamless integration of Tricentis Tosca with other tools and platforms. Driving continuous improvement in testing methodologies and practices. Providing leadership and mentorship to junior team members, fostering a culture of excellence. Contributing to the overall success and innovation of Synopsys technology offerings. What You ll Need: Minimum 7 years of experience in Tricentis Tosca automation with SAP, Salesforce, Oracle CPQ, APIs, Web applications, etc. Expertise in automating User Experience (UX) for Web-based, API, and Desktop applications, including Vision AI+. Proficient in Test Data management using Tricentis Data Services (TDS) and Tricentis Test Case Design (TCD). Experience in DEX Configuration & Execution. Ability to set up Continuous Integration/Continuous Deployment (CI/CD) pipelines with Tricentis Tosca. Expertise in QTest integration with Tosca Certifications TRICENTIS Certified SAP Testing Specialist TRICENTIS Certified Tosca Architect TRICENTIS Certified Automation Engineer TRICENTIS Certified QTest Specialist TRICENTIS Certified Test Design Specialis

* Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc ) * Generate verification test plan, verification environment documentation and test environment usage documentation * Define, develop, and verify complex UVM verification environments * Evaluates and exercises various aspects of the development flow. May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modelling, and verification coverage metrics (functional coverage and code coverage) * Collaborate with architect, designers , VIP team to accomplish tasks. * Identify design problems, possible corrective actions and/or inconsistencies on documented functionality * Work with peers to improve methodologies and improve execution efficiency. * Adhere to quality standards and good test and verification practices. * Work as a lead, mentor junior engineers, and help them in debugging complex problems. * Able to Support Customer issues, by their reproduction and analysis. * Should be able multitask between different activities. Key Qualifications * Proven desire to learn and explore new state of the art technologies * Demonstrate good written and spoken English communication skills * Demonstrate good review and problem-solving skills * Knowledgeable with Verilog, VHDL and/or SystemVerilog * Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus * Understanding of verification methodology such as UVM . * Good organization and communication skills * Be a solution provider. * 8+ years of relevant experience

Desired Skills and Experience: Proficiency with STA, SDC. Proficiency with RTL, System Verilog. Strong understanding of front-end EDA design methodologies. Strong Perl, Tcl or Python scripting skills. Prior experience with logic synthesis tools is required. Prior experience using or supporting SDC tools would be a significant plus. Prior experience with RTL simulation, SVA would be a plus. Prior experience supporting front-end EDA tools would be a plus. Sound communication skills, verbal and written. Ability to produce product requirement documents. BS EE/CE. 4 years experience with STA/Synthesis.

A minimum of 8 years of related experience. Excellent Software development experience with C / C++ on UNIX/Linux platforms Broad understanding of data structures, algorithms and their applications. Should have experience working in a multi-person product development environment with high dependencies and tight schedules. It is essential that the applicant is highly motivated and has solid desire to learn and explore new technologies. Demonstrated history of good analytical, debugging and problem-solving skills. Experience with complex software tool development and usage with legacy code base Exercise of judgment in developing methods, techniques, and evaluation criteria to meet project goals. Ability to work in both self-directed and collaborative settings. Understanding/Experience in Unified Power Format (UPF) would be beneficial Good written and oral communication skills, for team collaboration and product presentations. Preferred Skills: Special consideration given to those with background and experience in formal verification and/or synthesis techniques. Experience in Compilers and RTL Synthesis would be beneficial Knowledge of software specification and design process, and regression testing. Ability to know about customer wants and needs in the formal verification user community, by working with sales and field personnel.

Providing Customer Support and Collaborating with R&D teams to drive product development for wide deployment. Demonstrating differentiated PPA results to showcase our technologys superiority. Providing technical support to key global customers to address PPA bottlenecks and design challenges on the most advanced designs. Aggressively engaging in worldwide critical benchmarks and deployments to ensure the highest quality and performance of designs. Utilizing scripting languages such as Perl and Tcl for automation and optimization tasks. Staying updated with the latest advancements in ASIC design flow, VLSI, and CAD development to continually improve processes. The Impact You Will Have: Enhancing the performance and efficiency of Fusion Compiler designs. Driving innovations that contribute to the success of Synopsys cutting-edge technologies. Providing critical support that helps key customers overcome their PPA challenges. Contributing to the development of new features that keep Synopsys at the forefront of the industry. Improving the overall quality and reliability of our products through meticulous design and optimization. Fostering strong relationships with global customers, reinforcing Synopsys reputation as a leader in chip design and software security. What You ll Need: BS/MS in Electrical Engineering or Computer Science with 4+ years of relevant experience. Hands-on experience with synthesis and place and route (P&R) tools. Proficiency with EDA tools such as DC, FM, ICC2, and Fusion Compiler. Knowledge of advanced placement and routing rules. Experience with scripting languages like Perl and Tcl. Strong understanding of ASIC design flow, VLSI, and CAD development. Never give-up attitude and flexibility in supporting worldwide engagements. Who You Are: Excellent communicator with strong command of English. Highly motivated and self-driven. Detail-oriented with a focus on quality and performance. A team player who thrives in collaborative environments. Adaptable and eager to learn new technologies and methodologies.

Applications Engineer position offers a wonderful opportunity to work on most challenging technical problems in verification domain and innovative technologies under Synopsys Verification Platform. Looking for an experienced and motivated professional who enjoys problem solving, open to continuous learning, passionate to work on cutting edge technologies and has excellent communication skills. It gives exposure to the breadth of HDL/HVL, methodologies, static and formal verification, dynamic simulation aspects including debug and experience in working in a diverse environment where interaction with domain experts across global locations will be involved. Key Requirements Experience: Bachelors degree in Electronics with 7+ Years or Master s degree in Electronics with 5+ Years Experience in verification technologies (Simulation, UVM, SVA, LRM understanding) Strong HDL language support (Verilog, VHDL, System Verilog) Simulation, UVM, Design Verification Digital design fundamental and RTL coding understanding Good Debugging skills. Scripting - Perl, TCL, Make, Shell Scripting. Role - VCS Simulation Technology Product Engineer Solid fundamentals in Digital design, HDLs (Verilog/VHDL) and System Verilog Exposure to Synopsys EDA tools (SpyGlass, VC SpyGlass, Verdi) would be added advantage Excellent written and oral communication skills is a must as the role requires interfacing global teams, proposing solutions Must have working knowledge on UNIX, TCL and/or any other scripting language to be effective Team player, partners with multiple stakeholders, has attention to detail and innovative mindset Motivated, doer and self-organized team worker with good social communication skills Open to travel, ability to multi-task, be detail-oriented Drive VCS/related technology customer deployment working closely with field and R&D Drive competitive engagements, requirements gathering for delivery strong product roadmap Work directly with R&D, Product Validation & Customers to suggest improvements in implementation and validation Use in-depth product understanding to provide technical expertise, diagnose, troubleshoot issues

What You ll Need: BTech/MTech in Electrical Engineering or related field. Minimum of 3 years of experience with MTech or 5 years with BTech in CMOS circuit design and layout methodology. Strong knowledge of deep submicron process technologies and CMOS processes. Familiarity with JEDEC requirements for DDR interfaces and standards. Experience with ASIC design flow and ESD concepts is an advantage.

You are a passionate and meticulous Digital Verification Engineer with a keen interest in functional verification of High Speed interface IPs. With a dynamic personality and a strong eagerness to learn, you are driven to excel in Pre-silicon verification activities. Your understanding of digital design and HDL implementation sets you apart, and you thrive in environments where you can build and update verification plans and test cases . You are well-versed in scripting and automation using TCL, PERL, or Python , and possess excellent debug and diagnostic skills . Collaboration with digital designers is second nature to you, ensuring you achieve the desired coverage and performance in your projects. Your innovative mindset and commitment to excellence make you an invaluable asset to any verification team. What You'll Be Doing: Work on Functional Verification of High speed serial link PHY IPs for USBx, PCIex, Ethernet, Display & HDMI protocol standards. Study IP/design blocks/Firmware Specifications and build/update verification plans as well as the test cases. Build/update functional verification environments to execute the test plans. Implement checkers, assertions, random test generators, high level transactional models, and bus functional models (BFMs) as per the verification plan needs. Perform simulation, random and direct stimulus development, and coverage review. Work closely with digital designers for debug and achieve the desired coverage. The Impact You Will Have: Ensure the reliability and performance of High Speed interface IPs, critical to various advanced technologies. Contribute to the development of cutting-edge verification methodologies. Enhance the quality and efficiency of verification processes. Collaborate effectively with cross-functional teams to achieve project goals. Drive innovation in verification techniques, improving overall product quality. Support the creation of high-performance silicon chips that empower modern technology. What You'll Need: B.Tech/M.Tech with 3+ years of relevant experience. Understanding of functional verification flow with awareness of verification tools and methodologies such as VMM, OVM/UVM, and System Verilog. Proficiency in scripting and automation using TCL, PERL, or Python. Strong debug and diagnostic skills. Experience in building and updating verification environments and test plans.

What You'll Be Doing: Developing emulation solutions for industry-standard protocols such as AXI, AMBA, JTAG, AVB, CAN, and TSN. Engaging in software development using C/C++ and synthesizable RTL development using Verilog. Verifying emulation solutions to ensure they meet the highest standards of quality and performance. Interacting with customers during the deployment and debugging phases to provide technical support and ensure successful implementation. Collaborating with cross-functional teams to integrate emulation solutions with other Synopsys products and technologies. Continuously improving and optimizing emulation solutions to meet evolving industry needs and standards. The Impact You Will Have: Enhancing the efficiency and performance of semiconductor design processes through advanced emulation solutions. Contributing to the development of high-performance silicon chips and software content that drive technological innovation. Supporting semiconductor customers in overcoming design and verification challenges, leading to successful product launches. Improving the reliability and functionality of emulation solutions, thereby increasing customer satisfaction and trust in Synopsys products. Driving continuous improvement and innovation within the emulation solutions domain. Facilitating seamless integration of emulation solutions with other Synopsys technologies, enhancing overall product offerings. What You'll Need: Strong programming skills in C/C++ and understanding of OOPS concepts. Good understanding of digital design concepts. Knowledge of HDL languages such as System Verilog and Verilog. Experience with scripting languages like Perl or TCL is a plus. Understanding of ARM architecture is an added advantage. Knowledge of UVM and functional verification will be a plus.

What You ll Be Doing: Leading the digital verification flow for PVT Sensor Digital Verification. Setting up and managing AMS Verification and front-end Integration for MSIPs. Developing and supporting next-generation analog, digital, and mixed-signal IPs. Ensuring all blocks are verified for behavioral and functionality from top-level integration. Collaborating with a team to intercept TQV and other swim lanes for top-level integrations. Implementing mixed-mode simulations with significant improvements in execution time. The Impact You Will Have: Enhancing the reliability and performance of semiconductor lifecycle management solutions. Accelerating the integration of intelligent in-chip sensors and analytics capabilities. Optimizing performance, power, area, schedule, and yield for cutting-edge technology products. Reducing risk and time-to-market for differentiated products. Contributing to the development of Synopsys next-generation analog, digital, and mixed-signal IPs. Supporting the growth and success of Synopsys Sensor IP business unit. What You ll Need: BS or MS degree in Electrical Engineering, Computer Science, or Computer Engineering. 4-8 years of experience in design and verification for leading-edge Digital SOC chip design and IP development. Expertise in Digital Verification and/or AMS Verification with Verilog A and RNM. Proficiency in System Verilog and RNM (Real Number Modeling). Understanding of latest foundry PDKs and their usage in FE & BE flows. Who You Are: A detail-oriented and highly motivated verification engineer. A collaborative team player with excellent communication skills. A continuous learner eager to stay updated with industry trends and technologies. A leader capable of guiding and mentoring teams to achieve verification goals. A problem-solver with strong analytical and debugging skills. The Team You ll Be A Part Of: You will be a key member of Synopsys rapidly expanding Sensor IP business unit, working with a team of experts dedicated to developing and verifying next-generation analog, digital, and mixed-signal IPs. The team focuses on integrating intelligent in-chip sensors and analytics capabilities to enhance semiconductor lifecycle management solutions. Together, you will contribute to the success of Synopsys innovative technology products, driving the future of the semiconductor industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683Aschheim, GermanyEngineering Principal Analog Design EngineerMississauga, CanadaEngineering Verdi InternshipHsinchu, TaiwanInterns/Temp

Expertise in UVM and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective. Locally should be to be go-to person on all technical aspects of VIP At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683Aschheim, GermanyEngineering Principal Analog Design EngineerMississauga, CanadaEngineering Verdi InternshipHsinchu, TaiwanInterns/Temp

An experienced and motivated Senior R&D Engineer with a passion for developing cutting-edge technology solutions, you bring a strong background in Computer Science or Electronics and over 6 years of relevant experience. You possess the technical prowess and problem-solving skills needed to excel in this role. Your expertise in C/C++ programming, coupled with a deep understanding of SoC architectures and serial bus protocols, makes you a valuable asset to our team. You thrive in collaborative environments, demonstrate high energy, and are always willing to go the extra mile to achieve project success. Your strong communication skills and ability to prioritize tasks independently allow you to effectively guide junior team members and interact with customers, ensuring the successful delivery of high-quality solutions. What You'll Be Doing: Contributing to the modeling, integration, and testing of various peripherals within a SystemC-based platform modeling framework for diverse application domains such as Automotive and Wireless. Understanding IP modeling requirements and creating ESL model specifications. Effectively closing open technical issues to ensure project milestones are met. Guiding junior team members and consultants in projects involving SoC platform creation, validation, and software bring-up. Collaborating with cross-functional teams to ensure alignment and integration of virtual prototypes. Staying updated with the latest industry trends and advancements to continuously improve our development processes. The Impact You Will Have: Accelerating early software development and testing use cases for Automotive, Datacenter, AI, and Mobile products. Enhancing the accuracy and efficiency of virtual prototypes, leading to faster product development cycles. Providing critical insights and solutions to complex technical challenges, driving innovation within the team. Improving the overall quality and performance of our SoC modeling and simulation solutions. Supporting the seamless integration of various software applications and operating systems, such as Linux, Android, and AutoSar. Contributing to the success of high-profile projects that shape the future of technology and connectivity. What You'll Need: BE / B Tech / M Tech in Computer Science or Electronics with 6+ years of relevant experience. Proficiency in C/C++ programming. Excellent problem-solving skills. Experience in application development in assembly or higher-level languages. Understanding of SoC architectures and serial bus protocols like CAN, LIN, SPI, I2C (preferred). Experience in SoC peripherals modeling using C/C++/SystemC/HDL (preferred). Experience in multi-core-based platform developments (preferred). Who You Are: A high-energy individual with a willingness to go the extra mile. A team player with strong customer-facing skills. Possess excellent written and verbal communication skills. Demonstrate a high level of initiative and accountability towards assigned tasks. Ability to prioritize and work independently on multiple tasks. The Team You'll Be A Part Of: You will be part of an excellent development team in the System Level Design space. This team is involved in the creation of Virtual Prototypes (simulation models) for SoCs/MCUs/ECUs and the bring-up of Linux/Android/AutoSar OS/Embedded SW applications. Our focus is on catering to early Software Development Testing use cases for Automotive, Datacenter, AI, and Mobile products. We collaborate closely to drive innovation and deliver high-quality solutions that meet the evolving needs of our customers.

What You ll Need: Over 18 years of experience in IT HPC Engineering infrastructure management including Compute, Citrix, Storage, Networks, Data Centers. Experience with job scheduling and queuing systems like LSF, SLURM. Experience in handling large-scale 24X7 IT infrastructure delivery programs for global clients. Proven capability to translate business requirements into strategic programs and initiatives. Proficiency in building and managing large, high-functioning teams. Experience in different modules of SAP Success Factor, strategy, and roadmap development.

What You ll Be Doing: Designing and validating custom standard cells, including flip flops, clock gating cells, level shifters, and power gating cells. Optimizing standard cell circuits to achieve better performance, power, and area (PPA). Engaging in hands-on development while mentoring and coaching junior R&D engineers. Collaborating with layout designers to optimize layout parasitics and achieve target PPA. Involving in layout extraction and understanding layout-dependent parameters in the extracted netlist. Implementing, testing, and analyzing circuit design guidelines and methodologies. The Impact You Will Have: Driving innovations in standard cell design that contribute to the success of Synopsys products. Enhancing the performance, power, and area (PPA) of our silicon IP portfolio. Mentoring and developing the next generation of R&D engineers. Collaborating across functions to ensure methodology alignment and optimization. Contributing to the continuous improvement of circuit design methodologies. Supporting the integration of more capabilities into System-on-Chip (SoC) designs, meeting unique performance, power, and size requirements. What You ll Need: Bachelors or Masters degree in Electrical Engineering or a related field. 10+ years of experience in standard cell library design. Deep understanding of CMOS device characteristics and submicron process nodes. Experience with FINFET/GAA technologies and high sigma variation analysis. Familiarity with layout design and optimization of layout parasitics.

Floor planning, power planning, placement, and optimization Clock tree building and optimization Routing and optimization Timing constraints closure, synthesis, and formal verification Extraction, IR drop analysis, EM analysis, and signal integrity Physical verification and flow development for advanced technology nodes The Impact You Will Have:Enhance the best practices of the physical design flow Contribute to the successful implementation of high-performance digital designs Drive innovations in low-power design and high-speed clock distribution Ensure the integrity and reliability of complex IC designs Support the development of cutting-edge technology that shapes the future Collaborate with cross-functional teams to meet customer requirements What You ll Need:Solid engineering understanding of IC design concepts Strong knowledge of the full design cycle from RTL to GDSII Expertise in implementation flows and methodologies for deep sub-micron designs Experience in high-performance digital design, CAD, high-speed design, low-power design, and high-speed clock design and distribution Proven experience with project tape-outs and timing closure Proficiency in software and scripting skills (Perl, Tcl, Python) Knowledge of Synopsys tools, flows, and methodologies

You are a seasoned professional with a passion for GPU-accelerated systems and algorithm optimization With a strong background in computer science and extensive experience in GPU technologies like CUDA, OpenCL, or ROCm, you excel in designing and implementing high-performance solutions Your expertise in C++ and Python, along with your ability to troubleshoot and collaborate effectively, makes you an ideal fit for this role You are proactive, innovative, and always stay abreast of the latest trends in GPU technology Your ability to lead benchmarking and performance testing initiatives showcases your commitment to delivering optimal solutions for cutting-edge ILT software in the EDA industry, What Youll Be Doing: Optimize existing GPU implementations for ILT software, Design new GPU-accelerated algorithms for large-scale geometric data handling for ILT, Collaborate with cross-functional teams to ensure seamless integration of GPU features, Lead benchmarking and performance testing initiatives, Stay current on GPU technology trends and design the latest advancements into the system, Work closely with customers and hardware vendors to deliver optimal solutions rapidly, The Impact You Will Have: Enhance the performance and efficiency of ILT software through optimized GPU implementations, Develop innovative GPU-accelerated algorithms that handle large-scale geometric data efficiently, Ensure seamless integration of GPU features into existing Mask Synthesis tools, Lead performance testing to ensure the highest standards of software quality, Drive technological advancements by integrating the latest GPU trends into our systems, Contribute to the rapid manufacturing of new chips by delivering optimal solutions swiftly, What Youll Need: S 6+ years of experience working with GPU-accelerated systems, Proficiency in CUDA, OpenCL, ROCm, or related technologies, Expertise in C++ and Python, Experience in distributed computing environments, Strong troubleshooting and collaboration skills, Who You Are: Innovative and proactive with a keen interest in the latest GPU technologies, Detail-oriented with strong problem-solving skills, Effective communicator who excels in collaborative environments, Dedicated to delivering high-performance solutions and continuous improvement, Adaptable and able to thrive in a fast-paced, dynamic environment, The Team Youll Be A Part Of: You will be part of a highly skilled and collaborative team focused on developing and optimizing GPU-accelerated algorithms for ILT software Our team works closely with other cross-functional teams, customers, and hardware vendors to ensure the seamless integration of GPU features and the delivery of optimal solutions We are committed to staying at the forefront of technological advancements and driving innovation in the EDA industry, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring processYou are a seasoned professional with a passion for GPU-accelerated systems and algorithm optimization With a strong background in computer science and extensive experience in GPU technologies like CUDA, OpenCL, or ROCm, you excel in designing and implementing high-performance solutions Your expertise in C++ and Python, along with your ability to troubleshoot and collaborate effectively, makes you an ideal fit for this role You are proactive, innovative, and always stay abreast of the latest trends in GPU technology Your ability to lead benchmarking and performance testing initiatives showcases your commitment to delivering optimal solutions for cutting-edge ILT software in the EDA industry, What Youll Be Doing: Optimize existing GPU implementations for ILT software, Design new GPU-accelerated algorithms for large-scale geometric data handling for ILT, Collaborate with cross-functional teams to ensure seamless integration of GPU features, Lead benchmarking and performance testing initiatives, Stay current on GPU technology trends and design the latest advancements into the system, Work closely with customers and hardware vendors to deliver optimal solutions rapidly, The Impact You Will Have: Enhance the performance and efficiency of ILT software through optimized GPU implementations, Develop innovative GPU-accelerated algorithms that handle large-scale geometric data efficiently, Ensure seamless integration of GPU features into existing Mask Synthesis tools, Lead performance testing to ensure the highest standards of software quality, Drive technological advancements by integrating the latest GPU trends into our systems, Contribute to the rapid manufacturing of new chips by delivering optimal solutions swiftly, What Youll Need: S 6+ years of experience working with GPU-accelerated systems, Proficiency in CUDA, OpenCL, ROCm, or related technologies, Expertise in C++ and Python, Experience in distributed computing environments, Strong troubleshooting and collaboration skills, Who You Are: Innovative and proactive with a keen interest in the latest GPU technologies, Detail-oriented with strong problem-solving skills, Effective communicator who excels in collaborative environments, Dedicated to delivering high-performance solutions and continuous improvement, Adaptable and able to thrive in a fast-paced, dynamic environment, The Team Youll Be A Part Of: You will be part of a highly skilled and collaborative team focused on developing and optimizing GPU-accelerated algorithms for ILT software Our team works closely with other cross-functional teams, customers, and hardware vendors to ensure the seamless integration of GPU features and the delivery of optimal solutions We are committed to staying at the forefront of technological advancements and driving innovation in the EDA industry, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring processYou are a seasoned professional with a passion for GPU-accelerated systems and algorithm optimization With a strong background in computer science and extensive experience in GPU technologies like CUDA, OpenCL, or ROCm, you excel in designing and implementing high-performance solutions Your expertise in C++ and Python, along with your ability to troubleshoot and collaborate effectively, makes you an ideal fit for this role You are proactive, innovative, and always stay abreast of the latest trends in GPU technology Your ability to lead benchmarking and performance testing initiatives showcases your commitment to delivering optimal solutions for cutting-edge ILT software in the EDA industry, What Youll Be Doing: Optimize existing GPU implementations for ILT software, Design new GPU-accelerated algorithms for large-scale geometric data handling for ILT, Collaborate with cross-functional teams to ensure seamless integration of GPU features, Lead benchmarking and performance testing initiatives, Stay current on GPU technology trends and design the latest advancements into the system, Work closely with customers and hardware vendors to deliver optimal solutions rapidly, The Impact You Will Have: Enhance the performance and efficiency of ILT software through optimized GPU implementations, Develop innovative GPU-accelerated algorithms that handle large-scale geometric data efficiently, Ensure seamless integration of GPU features into existing Mask Synthesis tools, Lead performance testing to ensure the highest standards of software quality, Drive technological advancements by integrating the latest GPU trends into our systems, Contribute to the rapid manufacturing of new chips by delivering optimal solutions swiftly, What Youll Need: S 6+ years of experience working with GPU-accelerated systems, Proficiency in CUDA, OpenCL, ROCm, or related technologies, Expertise in C++ and Python, Experience in distributed computing environments, Strong troubleshooting and collaboration skills, Who You Are: Innovative and proactive with a keen interest in the latest GPU technologies, Detail-oriented with strong problem-solving skills, Effective communicator who excels in collaborative environments, Dedicated to delivering high-performance solutions and continuous improvement, Adaptable and able to thrive in a fast-paced, dynamic environment, The Team Youll Be A Part Of: You will be part of a highly skilled and collaborative team focused on developing and optimizing GPU-accelerated algorithms for ILT software Our team works closely with other cross-functional teams, customers, and hardware vendors to ensure the seamless integration of GPU features and the delivery of optimal solutions We are committed to staying at the forefront of technological advancements and driving innovation in the EDA industry, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process

You are a highly experienced and motivated professional with a solid background in SoC RTL Design With over 12 years of experience, you have honed your skills in RTL Design, Lint, CDC, RDC, Synthesis, and Constraints Development You possess a deep understanding of design concepts, ASIC flows, and stakeholder management Your technical expertise allows you to debug and diagnose violations and errors, set up flows and methodologies for RTL Signoff tools, and develop timing constraints You are an effective leader, capable of managing and growing a team, providing continuous feedback, and improving the quality of deliverables Your excellent communication skills help you interact with customers, peers, and management to understand needs, report status, and resolve issues efficiently, What Youll Be Doing: Manage and lead a team of 7-8 SoC/Subsystem RTL Design Engineers for various customer engagements, Work with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities, Lead the team to perform various RTL Design and Signoff activities for SoC Subsystems such as SoC u-Architecture and Integration, RTL Design (Verilog/SystemVerilog), Lint, CDC, RDC, Synthesis, Constraints Development, Assist and mentor the team in day-to-day activities and grow the capabilities of the RTL Design team for future assignments, Review various results and reports to provide continuous feedback to the team and improve the quality of deliverables, Report status to management and provide suggestions to resolve any issues that may impact execution, Understand the complexity and requirements of RTL Quality Signoff and propose resource requirements to complete the activities, Work with peers to improve methodology and improve execution efficiency, Collaborate with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tools, Train the team in design concepts and root-cause analysis, The Impact You Will Have: Drive the successful delivery of SoC Subsystems by leading a skilled team of RTL Design Engineers, Enhance the quality and efficiency of RTL Design and Signoff processes through continuous feedback and methodology improvements, Ensure customer satisfaction by understanding their needs and delivering high-quality solutions, Contribute to the growth and development of the RTL Design team, expanding their capabilities for future projects, Support Synopsysreputation as a leader in chip design and verification through successful project execution, Foster collaboration and innovation within the team and across different Synopsys departments, What Youll Need: E/B Technical expertise in various aspects of RTL Design and Signoff: LINT, CDC, RDC, Technical expertise on setting up flows and methodologies for quick deployment of RTL Signoff tools, Technical expertise in debugging and diagnosing violations and errors, Technical expertise in developing timing constraints and running preliminary synthesis for timing constraints check and area estimation, Ability to lead and manage a team to perform RTL Signoff on complex SoC/Subsystem, Experience with planning and managing various activities related to RTL Signoff and Design, Strong understanding of design concepts, ASIC flows, and stakeholders, Good communication skills, Who You Are: A proactive leader with excellent managerial skills, A team player who can mentor and guide engineers, An effective communicator who can interact with customers and stakeholders, A problem-solver with a keen eye for detail, An innovator who continuously seeks to improve processes, The Team Youll Be A Part Of: As part of the System Solutions Group (SSG), you will lead a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, and methodology to enable our customers to complete their most challenging SoC Design projects Our work spans from sub-blocks to full turnkey end-to-end SoCs Our customers range from start-ups to industry leaders, commercial companies, and government agencies, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,