Std. Cell/ Layout Engineers

As a Standard Cell Library Developer with 3+ years of relevant experience, you will be responsible for designing and optimizing standard cell libraries that contain logic gates like AND, OR, NAND, NOR, Flip-Flops with various drive strengths and functionality options. You will characterize standard cells by conducting static timing analysis (STA) to evaluate delay, power consumption, and other performance metrics under different process corners and operating conditions. Custom cell design will be required to create specialized standard cells for unique design requirements. Your role will involve generating physical layouts for standard cells using layout design tools such as Cadence Virtuoso and Synopsys IC Compiler. Running design rule checking (DRC) and layout versus schematic (LVS) verification will be essential to ensure that standard cell layouts comply with manufacturing design rules and match their schematics. Additionally, you will be responsible for characterizing and validating standard cell libraries for various technology nodes, ensuring consistency and accuracy. Implementing low-power standard cells with features like power gating and voltage scaling to optimize power consumption will be part of your responsibilities. You will need to address challenges specific to advanced process nodes like FinFET and multi-patterning when designing and optimizing standard cells. Collaboration with manufacturing teams will be necessary to guarantee that standard cell layouts are manufacturable, considering lithography, process variation, and yield. Maintaining detailed documentation of standard cell libraries, including timing models, power models, and layout guidelines, will be crucial. Your role will also involve working with digital design teams to integrate standard cell libraries into the overall chip design, ensuring seamless functionality and compatibility.,