Std. Cell/ Layout Engineers Digicomm Semiconductor

3.0 - 7.0 years

0 Lacs

karnataka

On-site

As a Standard Cell Library Developer with 3+ years of relevant experience, your role involves various key responsibilities: - Designing and optimizing standard cell libraries containing logic gates such as AND, OR, NAND, NOR, Flip-Flops with different drive strengths and functionality options. - Characterizing standard cells through static timing analysis (STA) to measure delay, power consumption, and other performance metrics under different process corners and operating conditions. - Creating custom cells or specialized standard cells as needed for unique design requirements. - Generating physical layouts for standard cells using layout design tools like Cadence Virtuoso, Synopsys IC Compi...

Posted 2 months ago

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Standard Cell Characterization Exiger Technologies

3.0 - 8.0 years

20 - 35 Lacs

bengaluru

Work from Office

We are looking for passionate and skilled Standard Cell Characterization Engineers to join our semiconductor design team in Bangalore. The role involves development, characterization, and validation of standard cell libraries to ensure optimal performance, power, and area (PPA). Responsibilities: Develop and support standard cell libraries. Perform PPA trade-off analysis between different cell architectures. Collaborate with layout team on floor plan, schematic, and layout guidelines. Design and implement combinatorial, sequential, and power management circuits. Run equivalence verification (e.g., ESPCV). Characterize and generate library views across multiple PVT corners. Support PnR, Simul...

Posted 3 months ago

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Std. Cell/ Layout Engineers Digicomm Semiconductor

3.0 - 7.0 years

0 Lacs

karnataka

On-site

As a Standard Cell Library Developer with 3+ years of relevant experience, you will be responsible for designing and optimizing standard cell libraries that contain logic gates like AND, OR, NAND, NOR, Flip-Flops with various drive strengths and functionality options. You will characterize standard cells by conducting static timing analysis (STA) to evaluate delay, power consumption, and other performance metrics under different process corners and operating conditions. Custom cell design will be required to create specialized standard cells for unique design requirements. Your role will involve generating physical layouts for standard cells using layout design tools such as Cadence Virtuoso...

Posted 4 months ago

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