Standard Cell Layout Design, Sr Engineer

As a Standard Cell Layout Design Senior Engineer at Digicomm Semiconductor Private Limited, you will be responsible for the following: - Minimum 6+ years of relevant circuit design experience in Standard Cell Layout Design. - Extensive experience in identifying, designing, and verifying cells to enhance core and SoC-level Performance, Power, and Area (PPA). - Strong understanding of MOSFET electrical behavior, transistor-level device physics, and PPA trade-offs, focusing on variability and layout challenges at advanced nodes like tsmc 3nm, Samsung 4nm, and below. - Expertise in transistor-level design of static circuits, including state-retaining elements such as latches and flip-flops. - Practical experience in developing and validating standard cell EDA views, including characterization, modeling, and quality assurance. - Proficient in using standard cell characterization tools and SPICE circuit simulators. - Skilled in scripting languages such as Perl or Python for design automation and data analysis. - Proven ability and willingness to mentor and support the growth of other team members. - Comfortable with iterative design processes and persistent in developing solutions to complex problems. - Consistently demonstrates a positive attitude and respect toward all team members. - Highly motivated to continuously expand technical expertise and take on diverse responsibilities to support the company's success. - Strong analytical skills with the ability to interpret data and communicate findings effectively. - Design and develop custom and semi-custom cells for advanced standard cell libraries. - Implement layout automation techniques to improve efficiency and streamline the development process. - Collaborate with cross-functional teams to ensure cohesive integration of design components across the flow. - Utilize EDA tools for schematic capture and layout design, targeting optimal performance and manufacturability. - Apply deep understanding of CMOS design principles and layout methodologies, focusing on advanced node technologies. - Develop and optimize layout solutions using programming languages such as C, Python, Perl, and UNIX scripting. Qualifications: - BTECH/MTECH Experience: - Engineers with 10+ years of experience Location: - Bangalore,