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Analog Devices
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Staff Engineer Digital Design Engineer

Staff Engineer Digital Design Engineer

Analog Devices

8 - 13 years

20 - 25 Lacs

bengaluru

Posted:13 hours ago| Platform:

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Skills Required

computer science automation digital design soc cad workflow healthcare perl python physical design

Work Mode

Work from Office

Job Type

Full Time

Job Description

Position : Staff Digital Design Engineer

Experience : 8+ years

Hiring Manager: Beorn Kiruba

Education : Bachelor/Masters engineering degree in Computer Science / Electrical / Micro-Electronics

Location : Bangalore, India

Job Grade : P4

Responsibilities:

Lead and develop Physical Design Methodologies emphasizing on best-in-class Methodologies for corporate wide digital flows using EDA tools from leading vendors like Cadence, Synopsys and Mentor Graphics
Work with global CAD methodology development team to automate and integrate the above CAD flows for centralized deployment
Provide strong technical expertise and consultations on place and route and rail analysis EDA flows to ADI s Business Units and ensure successful tapeouts of their products

Desired Skills:

Expertise in developing CAD Solutions in the areas of physical design using Cadence, Synopsys or Mentor Graphics EDA tool suite
Experience in overall digital implementation flows (RTL to GDS II) and has a well-proven track record of being involved in successful multi-million gate SOC design tapeouts in nanometer technology
Experience in low power design and implementation methodologies is desirable
Experience in working on sub 10nm technologies is desirable
Strong experience in automation of methodologies/solution using TCL, Python, PERL and Tk
Debugging experience to debug vendor tool problems and interacting with designers to help tackle their problems
Possess excellent interpersonal and communication skills to collaborate and influence design development groups across the globe

Position : Staff Digital Design Engineer

Experience : 8+ years

Hiring Manager: Jaikishan Gopal

Education : Bachelor/Masters engineering degree in Computer Science / Electrical / Micro-Electronics

Location : Bangalore, India

Job Grade : P4

Rssponsibilities:

Lead and develop timing methodologies, establish SDC constraints, and automate processes for special timing checks, ensuring design convergence and managing ECOs effectively.
Proficiency in performing static timing analysis (sign-off) for multi-corner, multi-voltage processes to align with PPA targets, at both block level and chip level, reviewing the timing arcs for the .lib generation.
Be responsible for constraint development, validation at the block/subsystem/full chip level.
Collaborate closely with Business Units and EDA vendors to ensure quality enhancements and address flow concerns thus enabling cutting edge signoff methodology.
Implement power-saving strategies, such as power gating, multi-voltage domains, and clock gating, to meet low-power objectives while preserving performance standards.
Create and refine custom scripts using Python, Tcl or Perl to enhance workflow efficiency and streamline Signoff design operations.
Mentor and support junior design engineers, disseminating best practices and providing technical guidance to elevate team proficiency and performance.

Desired Skills:

Proven ability in timing analysis, convergence, timing ECOs, and .lib generation on advanced technologies.
Proficient in industry standard Static Timing Analysis tools using Cadence or Synopsys toolsets
Understanding the timing requirements across Digital and Analog interfaces is a plus
Excellent problem-solving, leadership, and communication skills and values team culture.
Capable of thriving in fast-paced environments and good at multi-tasking.

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