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STA Synthesis Engineer

STA Synthesis Engineer

BAY Area Technology Solutions

2 - 6 years

7 - 11 Lacs

Hyderabad Bengaluru

Posted:3 weeks ago| Platform:

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Skills Required

STA Synthesis Engineering static timing analysis physical design concepts Verilog/VHDL ECO implementation

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Job Type

Full Time

Job Description

Position Description: STA (static timing analysis), Verilog/VHDL, and Synthesis will serve you well on our team. Showcase your deep understanding of the following physical design concepts/constraints: floor-planning, placement, congestion, and setup/hold timing closure. Embrace technical challenges with your natural passion to innovate. Ability to collaborate effectively with different functional teams and strong written/verbal communication. Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL transforms. Professional experience with ECO implementation, both functional and timing closure. Familiarity with simulation, debugging tools, and working closely with DV team. Experience with multi-clock and multi-power domain designs. Familiarity with DFT insertion, and multi-mode timing constraints. Position Requirements: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent Experience with full-chip static timing analysis through tapeout, gate level simulations, and Functional ECO implementation with Automated flows

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BAY Area Technology Solutions

www.bayareatechnologysolutions.com

Information Technology

San Francisco

50-100 Employees

60 Jobs

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Jane Doe

CEO
John Smith

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STA Synthesis Engineer

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Skills Required

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