Work from Office
Full Time
Experience with STA using Primetime and PTPX required Proficient in constraint generation. Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl scripting is required Strong problem solving and ASIC development/debugging skills. Experience with CPU micro-architecture and their critical path. Low power implementation techniques experience. High speed CPU implementation. Place and route tool experience. Constraint management tool and Verilog coding experience Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent
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Noida
6.0 - 8.0 Lacs P.A.