8 Sram Design Jobs

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work , to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! The Digital IP (DIP) group at NVIDIA is an organization of circuit design and CAD engineers that creates a wide variety of IP for the chips NVIDIA designs. This group works closely with internal SOC design, silicon testing, and productization teams that turn our IP into products that change the world. One of the roles fulfilled by the DIP group is to develop sophisticated SRAM compilers that are used extensively by our SOC design partners. We are looking to hire a skilled and creative SRAM circuit designer to help achieve these goals in a high-visibility position. What you'll be doing: Embedded SRAM design: Transistor-level circuit design, supervising layout implementation, physical and logical verification, and debug of SRAM macros. SRAM compiler development: Envisioning, defining, and coding more efficient ways to automate the simultaneous assembly and validation of multiple unique SRAM macros using NVIDIA's extensive compute resources. Advanced development: Exploring the potential of future process nodes and developing techniques to achieve optimal power, performance, and area characteristics. Guiding SOC design, silicon test, and productization efforts: Collaborate with SOC design partners to help them achieve their overall performance and cost goals, guide the silicon test and characterization efforts, and working with productization teams to prepare new silicon for the demanding requirements of real-world applications. What we need to see: BSEE minimum (or equivalent experience), MSEE or PhD preferred 5+ years of SRAM design experience with a strong background in digital circuit design, layout, and validation on advanced FinFET processes Prior design experience in single-port, dual-port, or register file SRAM-based macros required, including complex circuits like self-timed logic and sense-amplifiers Python scripting ability to parse data and automate tasks Successful track record of delivering designs to production Ways to stand out from the crowd: Self-motivation, attention to detail, and good written, verbal, and presentation skills are needed to success in this role A high degree of scripting expertise in Python Familiarity with Cadence schematic and layout capture tools Silicon testing/debug experience NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life's work, to amplify human imagination and intelligence. Make the choice, join our diverse team today! #LI-Hybrid

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work , to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! The Digital IP (DIP) group at NVIDIA is an organization of circuit design and CAD engineers that creates a wide variety of IP for the chips NVIDIA designs. This group works closely with internal SOC design, silicon testing, and productization teams that turn our IP into products that change the world. One of the roles fulfilled by the DIP group is to develop sophisticated SRAM compilers that are used extensively by our SOC design partners. We are looking to hire a skilled and creative SRAM circuit designer to help achieve these goals in a high-visibility position. What you'll be doing: Embedded SRAM design: Transistor-level circuit design, supervising layout implementation, physical and logical verification, and debug of SRAM macros. SRAM compiler development: Envisioning, defining, and coding more efficient ways to automate the simultaneous assembly and validation of multiple unique SRAM macros using NVIDIA's extensive compute resources. Advanced development: Exploring the potential of future process nodes and developing techniques to achieve optimal power, performance, and area characteristics. Guiding SOC design, silicon test, and productization efforts: Collaborate with SOC design partners to help them achieve their overall performance and cost goals, guide the silicon test and characterization efforts, and working with productization teams to prepare new silicon for the demanding requirements of real-world applications. What we need to see: BSEE minimum (or equivalent experience), MSEE or PhD preferred 3+ years of SRAM design experience with a strong background in digital circuit design, layout, and validation on advanced FinFET processes Prior design experience in single-port, dual-port, or register file SRAM-based macros required, including complex circuits like self-timed logic and sense-amplifiers Python scripting ability to parse data and automate tasks Successful track record of delivering designs to production Ways to stand out from the crowd: Self-motivation, attention to detail, and good written, verbal, and presentation skills are needed to success in this role A high degree of scripting expertise in Python Familiarity with Cadence schematic and layout capture tools Silicon testing/debug experience NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life's work, to amplify human imagination and intelligence. Make the choice, join our diverse team today! #LI-Hybrid

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work , to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! The Digital IP (DIP) group at NVIDIA is an organization of circuit design and CAD engineers that creates a wide variety of IP for the chips NVIDIA designs. This group works closely with internal SOC design, silicon testing, and productization teams that turn our IP into products that change the world. One of the roles fulfilled by the DIP group is to develop sophisticated SRAM compilers that are used extensively by our SOC design partners. We are looking to hire a skilled and creative SRAM circuit designer to help achieve these goals in a high-visibility position. What you'll be doing: Embedded SRAM design: Transistor-level circuit design, supervising layout implementation, physical and logical verification, and debug of SRAM macros. SRAM compiler development: Envisioning, defining, and coding more efficient ways to automate the simultaneous assembly and validation of multiple unique SRAM macros using NVIDIA's extensive compute resources. Advanced development: Exploring the potential of future process nodes and developing techniques to achieve optimal power, performance, and area characteristics. Guiding SOC design, silicon test, and productization efforts: Collaborate with SOC design partners to help them achieve their overall performance and cost goals, guide the silicon test and characterization efforts, and working with productization teams to prepare new silicon for the demanding requirements of real-world applications. What we need to see: BSEE minimum (or equivalent experience), MSEE or PhD preferred 5+ years of SRAM design experience with a strong background in digital circuit design, layout, and validation on advanced FinFET processes Prior design experience in single-port, dual-port, or register file SRAM-based macros required, including complex circuits like self-timed logic and sense-amplifiers Python scripting ability to parse data and automate tasks Successful track record of delivering designs to production Ways to stand out from the crowd: Self-motivation, attention to detail, and good written, verbal, and presentation skills are needed to success in this role A high degree of scripting expertise in Python Familiarity with Cadence schematic and layout capture tools Silicon testing/debug experience NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life's work, to amplify human imagination and intelligence. Make the choice, join our diverse team today! #LI-Hybrid

As a skilled and creative SRAM circuit designer at NVIDIA, you will play a crucial role within the Digital IP (DIP) group, an organization of circuit design and CAD engineers dedicated to creating a wide variety of IP for the chips NVIDIA designs. In this high-visibility position, you will be responsible for developing sophisticated SRAM compilers that are extensively used by our SOC design partners. Your responsibilities will include: - Embedded SRAM design: Engaging in transistor-level circuit design, overseeing layout implementation, conducting physical and logical verification, and debugging of SRAM macros. - SRAM compiler development: Conceptualizing, defining, and coding more efficient ways to automate the simultaneous assembly and validation of multiple unique SRAM macros using NVIDIA's extensive compute resources. - Advanced development: Exploring the potential of future process nodes and devising techniques to achieve optimal power, performance, and area characteristics. - Guiding SOC design, silicon test, and productization efforts: Collaborating with SOC design partners to help them meet their overall performance and cost objectives, leading the silicon test and characterization efforts, and working with productization teams to prepare new silicon for real-world applications. Requirements for this role include: - Minimum BSEE (or equivalent experience), MSEE or PhD preferred - 3+ years of SRAM design experience with a strong background in digital circuit design, layout, and validation on advanced FinFET processes - Prior design experience in single-port, dual-port, or register file SRAM-based macros required, including complex circuits like self-timed logic and sense-amplifiers - Proficiency in Python scripting for data parsing and task automation - Proven track record of delivering designs to production To excel in this role, self-motivation, attention to detail, and strong written, verbal, and presentation skills are essential. Additionally, a high level of scripting expertise in Python, familiarity with Cadence schematic and layout capture tools, and experience in silicon testing/debug are ways to stand out from the crowd. Join the diverse team at NVIDIA, where you will be immersed in a supportive environment that encourages everyone to achieve their best work and make a lasting impact on the world. Amplify human creativity and intelligence by contributing to our continuous evolution and innovation. Make the choice to be part of our team today and play a role in shaping the future of technology! JR1997194,

Role and Responsibilities SRAM design group in Bangalore develops various types of SRAMs, Registerfiles and ROMs in advanced technology nodes like 4nm, 2nm and beyond. The team is responsible for delivering highly competitive memories for the SAMSUNG Foundry customers. Provides a unique opportunity to the individuals who are willing to innovate and solve the most challenging problems in the field of circuit design. Samsung Foundry being a pioneer in new device technology, it creates ample opportunities for the circuit designer to innovate and design highly competitive IPs. Design highly competitive circuits to meet performance/power specifications requested by customers. Guide and lead a group of engineers to deliver the SRAM IP in the given timelines. Analyse circuits and identify potential robustness gaps and find solutions to improve robustness of the design. Own the responsibility from SPEC to GDS and DK delivery. Review circuits, robustness reports and identify potential robustness issues. Review layouts and suggest improvement areas to achieve competitive PPA. Understanding of SRAM PPA trade-offs and identify right techniques to meet SPEC. Must be able to communicate effectively across different teams. Skills and Qualifications Master/Bachelor in electronics Working experience (10+ years) preferably in Memory design Understanding of RC network and FinFET fundamentals are necessary Custom or Compiler SRAM/ROM development experience Fundamentals of process variability and its effect on memory design Thorough understanding of SRAM bit cell and its characteristics (Read current, Standby current, data retention, SNM) Strong understanding of circuit design fundamentals Critical path modeling concept, various types of models (RC, C, Pi, ladder) Good knowledge of semiconductor physics, like knowledge of FinFET function, parasitics etc Analysing layout and understanding of LLE effects Bachelor's / Master degree in Computer Science, Electrical/Electronics Engineering, Engineering and 10+ years of experience in circuit design

What You'll Be Doing: Develop CMOS embedded memories such as SP SRAM, DP SRAM, Register File, and ROM. Design architecture and circuit implementation, focusing on ultra high speed, ultra low power, or high density designs. Perform schematic entry, circuit simulation, layout planning, layout supervision, design verification, and validation. Interface with CAD and Frontend engineers for memory compiler automation, EDA model generation, and full verification flow. Perform bit cell development and verification, and drive physical layout design and verification. Provide support and/or perform other duties as assigned and required. The Impact You Will Have: Contribute to the development of high-performance silicon chips and software content. Enhance the efficiency and performance of our CMOS memory designs. Drive innovation in ultra high speed, ultra low power, and high density memory designs. Ensure the highest quality in bit cell development and physical layout design. Collaborate effectively with CAD and Frontend engineers to streamline automation and verification processes. Support the continuous improvement and advancement of our memory design technology. What You'll Need: Bachelor's or Master's degree in Electrical Engineering, Telecommunication, or related fields. Proficiency in CMOS memory design, circuit simulation, memory layout designs, layout parasitic extraction, and layout verification tools and debugging techniques. Programming capability in C-Shell and Perl; knowledge of C++ or Java script is a plus. Strong analytical and problem-solving skills with attention to detail. Experience in developing documents, reports, or presentations for a range of tasks. Who You Are: Self-motivated, self-directed, detail-oriented, and well-organized. Possess excellent analytical, problem-solving, and negotiation skills. Capable of leading and mentoring trainees and junior engineers, as well as managing projects. Strong command of English, both verbal and written. Exhibit strong interpersonal communication and teamwork skills. Professional, critical/logical thinker, and focused on future goals. Highly committed to continuous learning and professional development.

What You'll Be Doing: Designing, developing, and troubleshooting embedded memory compilers. Applying skills in memory compilers, focusing on transistor-level circuit design. Understanding various memory design aspects such as read/write margins and timing races to find effective solutions. Interacting with the layout team to address and resolve issues from both design and layout standpoints. Working independently on tasks, ensuring ownership and collaboration to achieve optimal results. Engaging frequently with senior personnel to leverage expertise and enhance project outcomes. The Impact You Will Have: Enhancing the performance and reliability of embedded memory compilers. Driving innovation in memory design, contributing to the development of high-performance silicon chips. Collaborating with cross-functional teams to optimize design and layout processes. Ensuring timely delivery of robust and efficient memory solutions. Contributing to the continuous improvement of design methodologies and practices. Supporting the advancement of Synopsys technology leadership in the semiconductor industry. What You'll Need: 2-5 years of experience in Embedded SRAM compilers. Strong understanding of CMOS digital circuits. Knowledge of FinFET technology (preferred). Proficiency in transistor-level circuit design. Ability to analyze and resolve design and layout issues effectively. Who You Are: Innovative and detail-oriented. Collaborative team player. Effective communicator with strong interpersonal skills. Problem-solver with a proactive approach. Self-motivated and able to work independently.

Introduction As a Hardware at , youll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in todays market. Your role and responsibilities -Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelors Degree Preferred education Masters Degree Required technical and professional expertise -12+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.