Sr. Silicon Design Engineer

Advanced Micro Devices, Inc

5 - 10 years

25 - 30 Lacs

hyderabad

Posted:1 day ago| Platform:

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Skills Required

sta automation timing closure dft front end soc silicon ips gaming recruitment

Work Mode

Work from Office

Job Type

Full Time

Job Description

THE ROLE:

The focus of this role is to plan and execute the front end implementation of IPs and its closure. This involves ownership of synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. Guide team members on technical issues.

KEY RESPONSIBILITIES:

Responsible for front end implementation of IPs which includes synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure
Collaborate with designer and PNR teams to achieve closure.
Understand duration required, plan and execute as per schedule.
Complete quality delivery for synthesis and timing closure.
Debug and resolve technical issues

PREFERRED EXPERIENCE:

Highly experienced in synthesis, LEC, CLP and timing closure
Preferred top level or SOC level experience
Have handled blocks with complex designs, high frequency clocks and complex clocking
complete understanding of timing constraints, low power aspects and concepts of DFT
Have debug experience to solve issues.
scripting and automation

ACADEMIC CREDENTIALS:

Bachelors with 5 years of experience or Masters degree with 3 years of experience in Electrical Engineering

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