SoC Static Timing Analysis Engineer

As a member of the team at Google, you will play a crucial role in developing custom silicon solutions for Google's direct-to-consumer products, contributing to the innovation that impacts millions globally. Your expertise in electrical engineering or computer science will be instrumental in shaping the future of hardware experiences, focusing on performance, efficiency, and integration. **Key Responsibilities:** - Create design constraints based on architecture/microarchitecture documents, understanding various external IO protocols. - Validate design constraints across multiple corners/modes using Fishtail/Timevision. - Utilize Primetime for running and validating constraints post synthesis runs, setting up timing constraints, and defining the overall static timing analysis (STA) methodology. - Collaborate with the design team and block owners to ensure sign-off timing convergence throughout the project. - Implement constraints promotion and demotion flow using Fishtail and Timevision. - Assess various timing methodologies/tools on different designs and technology nodes, working on automation scripts within STA or tools for methodology development. **Qualifications Required:** - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. - 8 years of experience with Static Timing Analysis, Constraints development and validation, sign-off corner definitions, process margining, and setup of frequency goals with technology growth and platform development kit (PDK) changes. **Preferred Qualifications:** - Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science. - Proficiency in a scripting language like Perl or Python. - Experience in developing constraints and validating using Timing Constraints Manager (e.g., Synopsys) or TimeVision (e.g., Ausdia). By joining Google's Silicon team, you will be involved in developing hardware and software to support Google's ASIC innovations, driving the complete design constraints development process, working on sign-off timing convergence, and contributing to the advancement of computing infrastructure. Your work will be pivotal in delivering cutting-edge technologies that enhance the computing experience for users worldwide.,