SoC Senior Design and Integration Engineer

In this role, you will work to shape the future of AI/ML hardware acceleration, specifically focusing on TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You will be part of a team that pushes boundaries and develops custom silicon solutions for Google's TPU, contributing to the innovation behind products loved by millions worldwide. Your expertise in design and verification will be utilized to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. Key Responsibilities: - Own microarchitecture, implementation, and integration of SoC Chassis and subsystems. - Perform quality check flows like Lint, CDC, RDC, VCLP. - Drive design methodology, libraries, debug, and code review in coordination with other IPs Design Verification (DV) teams and physical design teams. - Identify and drive power, performance, and area improvements for the domains owned. Qualifications Required: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. - 5 years of experience in ASIC/SoC development with Verilog/SystemVerilog. - Experience in one or more SoC Integration domains and flows (Clocking or debug or fabrics/NoC or Security or low power methodologies). - Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Preferred Qualifications: - Experience with programming languages (e.g., Python, C/C++ or Perl). - Experience in SoC designs and integration flows. - Knowledge of bus architectures, fabrics/NoC or memory hierarchies. - Knowledge of high performance and low power design techniques. If you join this team, you will be part of a group developing SoCs used to accelerate machine learning computation in data centers. Your role will involve solving technical problems with innovative logic solutions and evaluating design options with complexity, performance, power, and area considerations. Collaboration with members of architecture, verification, power and performance, physical design, and other teams will be essential to specify and deliver high-quality designs for next-generation data center accelerators.,