4 Smartnics Jobs

Join our ambitious team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our mission is to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You will have the opportunity to work on groundbreaking products and collaborate with talented hardware and software engineers to create disruptive infrastructure solutions that excite our customers. We are seeking talented engineers experienced in physically implementing large-scale networking and computing semiconductor products. You will be part of a dynamic startup environment and contribute to the full lifecycle of complex chip development, from CAD tool flow setup to physical verification and tapeout. This role is based in India, with options for hybrid/remote work. Candidates capable of in-office participation in Hyderabad or Bangalore are preferred. Responsibilities: - Develop and maintain the CAD tool flow for physical implementation in a cloud-first environment. - Collaborate with architects on chip-level floorplan and block partitioning, considering tradeoffs in functional partitioning and interface complexity. - Design major physical structures like clock architecture, power delivery network, and interconnect topologies. - Execute physical implementation at block, cluster, and top levels, including synthesis, floorplan, timing closure, and tapeout. - Liaise with foundry and library partners on 3rd party IP integration and process technology issues. Skills/Qualifications: - Proven track record in physical implementation of high-performance network switching/routing fabrics, NICs, CPUs, or GPUs in the latest silicon process nodes. - Proficiency in CAD tools like Cadence Genus, Synopsys ICC2, and analysis tools such as Redhawk. - Experience with scripting languages like Perl, Python, and SystemVerilog. - Minimum BSEE/CE + 10 years or MSEE/CE + 5 years experience with products shipped in high volume. Company Background: We are a well-funded startup based in Mountain View, CA, founded by industry veterans and backed by top-tier investors. Our diverse team excels in co-designing hardware/software solutions and has a proven track record in processing global data center traffic. Note: The above job description is based on the mentioned details in the provided job description.,

General Overview Job Title: Staff Engineer, Software Functional Area: Engineering (ENG) Career Stream: Design - Software Engineering Job Code: SEN-ENG-DSE Job Band: 10 Direct/Indirect Indicator: Indirect Summary The Staff Engineer, Software develops, debugs, tests, deploys and supports code to be deployed in systems/products/equipment for various applications. They write, debug, maintain, and test software in various common languages and for software at various levels in the hierarchy (from Firmware to Application). Software creation follows an agreed to development process (such as Agile, Scrum, etc.) and complies with the product life cycle development (phase/gate deliverables). The Staff Engineer, Software works in cross functional teams with other designers, customers, manufacturing engineering and project leadership to ensure robust and high quality product development. Enhance designs with feedback from reviews in areas such as manufacturing, test, supply chain, reliability, industrial design and simulations. Detailed Description Provides technical leadership to the compute team team Develops and reviews Linux device drivers (I2C, SPI, LPC, PCIE etc.) and diagnostic firmware for manufacturing tests and for extended testing at assembly and deployment locations Releases the documents work according to procedures and the design specification to the team. Manages the software change by using software revision control and issue tracker tools. Participates in technical discussion, review of other team members artifacts, code etc Knowledge/Skills/Competencies Strong programming skills:Proficiency in C, C++, P4 and other low-level programming languages Hardware experience:Familiarity with main elements of CPU, DPU, memory, NICs, board monitoring elements is a must Experience with GPU programming:Prior experience with GPU libraries like CUDA and ROCm Networking knowledge:Deep understanding of networking protocols (TCP/IP, Ethernet, etc.) and concepts Debugging and testing skills:Ability to identify and resolve software and hardware issues. Problem-solving skills:Strong analytical and problem-solving abilities Experience with SmartNICs:Prior experience developing software for SmartNICs and understanding of cloud computing architectures and services is the plus Clear Communication: Proven ability to articulate requirements and vision to large and diverse audience through written documents like architecture specifications and verbal presentations in technical forums is required. Physical Demands Duties of this position are performed in a normal office environment. Duties may require extended periods of sitting and sustained visual concentration on a computer monitor or on numbers and other detailed data. Repetitive manual movements (e.g., data entry, using a computer mouse, using a calculator, etc.) are frequently required. Occasional travel may be required. Typical Experience 10 to 15 years Typical Education Bachelor degree or consideration of an equivalent combination of education and experience. Educational Requirements may vary by Geography Notes This job description is not intended to be an exhaustive list of all duties and responsibilities of the position. Employees are held accountable for all duties of the job. Job duties and the % of time identified for any function are subject to change at any time.

You will be joining NVIDIA as a Senior Power Verification Engineer, where you will be responsible for verifying the design and implementation of low power features for Smart-NICs and DPUs. These cutting-edge networking processors aim to accelerate network performance, reduce CPU overhead in IP packet transport, and optimize processor cycles for running applications efficiently. The Networking Chip Design team in India is rapidly expanding, offering an exciting opportunity to work on innovative projects in a fast-paced environment. Your key responsibilities will include working on structural and functional verification of low power aspects of NVIDIA's smartNICs and DPUs. You will develop test plans, coverage plans, and test cases, along with test bench components like assertions and coverage points. Collaborating with system and unit level teams, you will ensure comprehensive coverage of features from various aspects such as functional, electrical, performance, and noise. Additionally, you will analyze power consumption by unit IPs through debugging waves and work closely with cross-functional teams to achieve verification convergence. To qualify for this role, you should have a BS/MS or equivalent experience specializing in Low Power techniques and Verification, along with at least 5 years of relevant experience. A strong understanding of power basics, power intent formats, and experience with power check and verification tools is essential. Familiarity with low power design techniques and verification environments will be advantageous for this position. To distinguish yourself as a candidate, prior experience with SmartNICs or high-speed interconnects, proficiency in programming languages such as Python, Perl, or C++, and strong problem-solving skills will be beneficial. Demonstrating good interpersonal skills and a collaborative mindset to work effectively as part of a team will set you apart in this role. NVIDIA is recognized as one of the most sought-after employers in the technology industry, offering competitive salaries and a comprehensive benefits package. As you consider your career growth, explore the opportunities and benefits NVIDIA provides for you and your family at www.nvidiabenefits.com.,

Key Responsibilities : End-to-End Architecture : Lead the greenfield architecture and design of the entire L2/L3 networking stack, including the data plane (Fast Path) and control plane interactions, for a new platform. Core Protocol Development : Develop high-performance, scalable, and robust code in Embedded C on Linux for the data plane, focusing on L2/L3 forwarding and feature implementation. L4-L7 Service Integration : Design, implement, and integrate critical L4-L7 protocols with a mandatory focus on OpenSSL, NAT, IPsec, and MacSec. NOS Expertise : Leverage your deep understanding of Network Operating System (NOS) internals to ensure seamless integration, performance tuning, and system stability. Line-Rate Processing : Implement logic for line-rate packet processing, including specific requirements for regular expression (RegEx) matching in the data path. Container Networking : Architect and integrate solutions for container networking, ensuring efficient and scalable connectivity for modern applications. Validation & Performance Tuning : Utilize traffic generation tools like IXIA to perform rigorous performance validation, stress testing, and functional verification of the entire software stack. Technical Leadership & Mentorship : Act as the senior technical authority. Mentor engineers, lead design reviews, and establish a center of excellence for network protocol development within the team. Required Skills & Qualifications (Must-Haves) : Experience : 12-18 years of hands-on experience in network protocol development, with a proven track record of architecting complex networking software. Programming : Expert-level proficiency in Embedded C and a strong command of the Linux development environment. NOS Internals : Exhaustive, hands-on knowledge of NOS internals, control plane/data plane separation, and Fast Path / data plane acceleration techniques. L2/L3 Protocols : Deep, architectural understanding of L2 switching (VLANs, STP, LACP) and L3 routing (OSPF, BGP, VRF, ECMP). L4-L7 Mandatory Protocols : Demonstrable, deep implementation experience with the following : OpenSSL (Integration, session management, crypto offload) NAT (SNAT, DNAT, connection tracking) IPsec (Tunnel/Transport mode, IKEv1/v2, ESP/AH) MacSec (IEEE 802.1AE) IP Networking Stack : Comprehensive knowledge of the IP networking stack (TCP/IP, UDP) and packet flow through a system. Testing Tools : Proven experience using IXIA or Spirent for creating complex traffic profiles, performance benchmarking, and debugging. Container Networking : Solid understanding of container networking concepts (e.g., CNI, veth pairs, network namespaces, overlays). Desired Skills & Qualifications (Nice-to-Haves) : Experience with network processors, DPUs, or SmartNICs (e.g., Broadcom, Marvell, NVIDIA). Proficiency in Python for automation and testing. Familiarity with hardware-accelerated regex engines. Prior experience in a customer-facing or solutions architect role.