Silicon Design Engineer 2

2 - 7 years

20 - 25 Lacs

Posted:1 day ago| Platform: Naukri logo

Apply

Work Mode

Work from Office

Job Type

Full Time

Job Description

KEY RESPONSIBILITIES:

  • Responsible for front end implementation of physical partition which includes synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure
  • Collaborate with designer and PNR teams to achieve closure.
  • Complete quality delivery for synthesis and timing closure.
  • Debug and resolve technical issues

PREFERRED EXPERIENCE:

  • Experienced in synthesis, LEC, CLP and timing closure
  • Have handled blocks with complex designs, high frequency clocks and complex clocking
  • complete understanding of timing constraints, low power aspects and concepts of DFT
  • Have debug experience to solve issues.
  • scripting and automation

ACADEMIC CREDENTIALS:

  • Bachelors with 2 years of experience or Masters degree with 1 year of experience in Electrical Engineering

Mock Interview

Practice Video Interview with JobPe AI

Start Job-Specific Interview
cta

Start Your Job Search Today

Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.

Job Application AI Bot

Job Application AI Bot

Apply to 20+ Portals in one click

Download Now

Download the Mobile App

Instantly access job listings, apply easily, and track applications.

coding practice

Enhance Your Skills

Practice coding challenges to boost your skills

Start Practicing Now
Advanced Micro Devices, Inc logo
Advanced Micro Devices, Inc

Semiconductors

Sunnyvale

RecommendedJobs for You

hyderabad, telangana, india

hyderabad, telangana, india

hyderabad, telangana, india

hyderabad, telangana, india

hyderabad, telangana, india