Job
Description
As a SERDES Senior/Staff Designer at Ceremorphic AI, you will be responsible for a core part of the high-speed PHY, including PCIe, Ethernet, and USB, in advanced FinFet technology nodes. Your role will involve utilizing your strong understanding of analog/mixed-signal circuit theories and expert hands-on design skills to contribute to the success of our system. Key Responsibilities: - Demonstrating a strong understanding of analog/mixed-signal design theories and practical concepts such as mismatch, ratio-metric, linearity, stability, noise, and low-power - Having a strong understanding of one of the following core components of a high-speed PHY: CDR, PLL, PI, CTLE, TX Driver, Serializer/De-Serializer - Conducting circuit tradeoff analysis and comprehending system-level specs and their impacts on circuit design, with knowledge of PAM4 systems being a plus - Understanding the physical layout requirements and having hands-on ability to perform critical layouts, with experience in FinFet being advantageous - Showcasing a proven track record of successful tape out and silicon meeting performance and power specifications, along with experience in chip debug/validation/characterization - Communicating technical issues effectively and presenting technical reviews coherently and logically Qualifications Required: - Strong understanding of analog/mixed-signal design theories and practical concepts - Expertise in one of the core components of a high-speed PHY - Experience in circuit tradeoff analysis and system-level specs comprehension - Ability to perform critical layouts and experience with FinFet technology - Proven track record of successful tape out and silicon meeting performance and power specifications - Strong communication skills for presenting technical reviews effectively and logically If there are any additional details about the company in the job description, please provide them. As a SERDES Senior/Staff Designer at Ceremorphic AI, you will be responsible for a core part of the high-speed PHY, including PCIe, Ethernet, and USB, in advanced FinFet technology nodes. Your role will involve utilizing your strong understanding of analog/mixed-signal circuit theories and expert hands-on design skills to contribute to the success of our system. Key Responsibilities: - Demonstrating a strong understanding of analog/mixed-signal design theories and practical concepts such as mismatch, ratio-metric, linearity, stability, noise, and low-power - Having a strong understanding of one of the following core components of a high-speed PHY: CDR, PLL, PI, CTLE, TX Driver, Serializer/De-Serializer - Conducting circuit tradeoff analysis and comprehending system-level specs and their impacts on circuit design, with knowledge of PAM4 systems being a plus - Understanding the physical layout requirements and having hands-on ability to perform critical layouts, with experience in FinFet being advantageous - Showcasing a proven track record of successful tape out and silicon meeting performance and power specifications, along with experience in chip debug/validation/characterization - Communicating technical issues effectively and presenting technical reviews coherently and logically Qualifications Required: - Strong understanding of analog/mixed-signal design theories and practical concepts - Expertise in one of the core components of a high-speed PHY - Experience in circuit tradeoff analysis and system-level specs comprehension - Ability to perform critical layouts and experience with FinFet technology - Proven track record of successful tape out and silicon meeting performance and power specifications - Strong communication skills for presenting technical reviews effectively and logically If there are any additional details about the company in the job description, please provide them.
