Posted:12 hours ago|
Platform:
Work from Office
Full Time
Key Skills: Asic Verification, System Verilog, Verilog, PCI, Ethernet Roles and Responsibilities: Verify a block or a functional feature and lead it to closure. Write and architect scalable and reusable testbenches from scratch, using the framework of the verification methodology. Create test cases, functional coverage models, and bring the verification to closure. Think differently and out-of-the-box to stress the DUT and verify it in an efficient way. Be involved in documenting the verification strategy including test plans, verification micro-architecture, coverage objects, etc. Participate in and own verification strategic decisions that will help in the long run. Skills Required: Deep understanding of the full ASIC cycle, from conceptualization to TapeOut. Strong experience writing and debugging test benches. Proficiency in constrained random verification methodologies like UVM, VMM, or OVM. Strong knowledge of SystemVerilog. Solid command over object-oriented programming (OOP) principles. Open to learning and applying innovative verification methodologies and strategies. Motivated, self-driven, and able to work independently. Education: Bachelor's or BE degree in Engineering.
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