Senior Verification Architect – Simulation & Methodology

WHAT YOU DO AT AMD CHANGES EVERYTHING

Together, we advance your career.

MTS SILICON DESIGN ENGINEER

THE ROLE:

AMD

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

The successful candidate will assume technical responsibilities and hands-on technical architect role responsible for providing complex design methodologies in the hardware design verification space. The following is a list of key responsibilities that the candidate will assume:

• • Be a part of a wider team of technical experts in design verification and testbenches in AMD's Central R&D team
  • Be hands on technical contributor in the space of hardware description languages such as Verilog, testbench languages such as SystemVerilog
  • Play an expert role in verification methodologies and have extensive knowledge on UVM based testbenches
  • Possess and utilize in-depth knowledge in functional and code coverage technology and methodology to achieve faster coverage closure
  • Drive methodology around SOC/IP verification, VIPs, UVCs and BFMs
  • Demonstrate and utilize strong debugging skills in industry standard SOC/IP design & verification tools
  • Have knowledge of Verification Management tools and methodologies
  • Play a strong role in understanding AMD's existing systems, creating new ones, defining roadmaps on all verification methodologies, tools and flows
  • Knowledge of C/C++ based testbench architectures
  • Develop flows and methodology to integrate multiple independent testbenches/designs into a larger design and verification model
  • Simulation Performance analysis of existing designs, testbenches to keep up with the growing design sizes

PREFERRED EXPERIENCE:

• 7+ years of experience
• Proficient in IP level ASIC verification
• Proficient in debugging firmware and RTL code using simulation tools

• Proficient in using UVM testbenches and working in Linux and Windows environments
• Experienced with Verilog, System Verilog, C, and C++
• Graphics pipeline knowledge
• Developing UVM based verification frameworks and testbenches, processes and flows
• Automating workflows in a distributed compute environment.

• Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
• Strong background in the C++ language, preferably on Linux with exposure to Windows platform
• Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
• Good working knowledge of SystemC and TLM with some related experience.
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.

• Exposure to leadership or mentorship is an asset
• Desirable assets with prior exposure to video codec system or other multimedia solutions.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

#LI-PK2

Benefits offered are described: .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.