Senior Static Timing Analysis Engineer

As a Senior Static Timing Analysis Engineer at MosChip Technologies, located in Hyderabad, you will play a crucial role in ensuring that designs meet performance criteria by performing static timing analysis, synthesis, and logical equivalence checking (LEC). Your responsibilities will include failure analysis, debug, and providing design optimizations. You will collaborate with cross-functional teams to evaluate and enhance chip performance by analyzing data and running simulations. Key Responsibilities: - Conduct Static Timing Analysis (STA), Synthesis, and Logical Equivalence Checking (LEC) to ensure design performance. - Utilize strong analytical skills for failure analysis and data analysis. - Run simulations and testing methodologies to enhance chip performance. - Develop design constraints and check timing paths up to 2GHz for high-speed digital designs. - Utilize Fusion Compiler for synthesis and optimization. - Perform post-layout Static Timing Analysis (STA) for final sign-off. - Analyze Signal Integrity and Power Integrity, including crosstalk and IR drop effects. - Apply chip finishing methodologies and industry-standard EDA tools for STA. - Demonstrate solid knowledge of physical design concepts and excellent problem-solving skills. Qualifications: - Proficiency in Static Timing Analysis (STA), Synthesis, and Logical Equivalence Checking (LEC). - Strong analytical skills with experience in failure analysis and data analysis. - Expertise in running simulations and testing methodologies. - Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field and 7+ years of experience in STA closure for complex digital designs. - Proven experience in checking timing paths up to 2GHz for high-speed digital designs. - Hands-on expertise with Fusion Compiler for synthesis and optimization. - Demonstrated proficiency in performing post-layout Static Timing Analysis (STA) for final sign-off. - Design Constraints Development. - Proven expertise in Signal Integrity and Power Integrity analysis, including understanding of crosstalk and IR drop effects. - Solid knowledge of chip finishing methodologies and experience with industry-standard EDA tools for STA. - Strong understanding of physical design concepts and excellent problem-solving skills.,