Senior Staff Physical Design Engineer

General Summary: Qualcomm is a global technology leader driving innovation to enable next-generation experiences and digital transformation for a smarter, connected future. As a Hardware Engineer specializing in Physical Design (PNR), you will take full ownership of the physical implementation of Qualcomm SoCs. This includes floor planning, placement, clock tree synthesis (CTS), optimization, signoff activities, and overall chip physical design flow on advanced process nodes (4nm, 5nm, 7nm, 10nm). You will collaborate with cross-functional teams to optimize performance, power, and area (PPA), and ensure robust timing closure and design integrity. This role demands strong expertise in state-of-the-art physical design flows, signoff methodologies, and scripting automation on Unix/Linux environments. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 6+ years of related Hardware Engineering experience. OR Master's degree with 5+ years experience. OR PhD with 4+ years experience. For this senior role, 12+ years of hands-on experience in PNR physical design on advanced technology nodes (4nm, 5nm, 7nm, 10nm) is required. Required Skills & Expertise: Expertise in floorplanning, placement, clock tree synthesis (CTS), routing, post-route optimization for complex SoCs. Deep understanding of signoff domains and methodologies including: STA (Static Timing Analysis) Power analysis Formal Verification (FV) Low Power Verification Physical Verification (PV) Logical Equivalence Checking (LEC) Clock Latency Programming (CLP) Power Distribution Network (PDN) Strong proficiency with Unix/Linux environments and scripting languages, especially Perl and TCL for automation and flow customization. Ability to work independently with strong analytical and problem-solving skills. Proven track record delivering physical implementation on leading-edge semiconductor process nodes. Principal Duties and Responsibilities: Own the complete Physical Design flow for Qualcomm SoCs, including floorplanning, placement, CTS, routing, and signoff. Collaborate closely with timing, power, verification, and backend teams to achieve timing closure and meet power and area goals. Drive process improvements and automation in the physical design flow using scripting and tool customization. Troubleshoot complex design issues related to timing, power, and signal integrity. Maintain up-to-date knowledge of the latest industry tools and methodologies for physical design. Mentor junior engineers and contribute to team knowledge sharing.