Senior STA Engineer

About The Role

About The Role :

Your responsibilities may include but not be limited to:

STA setup, convergence, reviews and sign-off for Multi-Mode and Multi-corner Multi voltage domain designs. Timing analysis and Timing Closure at Partition/Sub-system/FC level.

Develops and defines methodologies to ensure highest quality of timing models that enable the physical design team to operate efficiently.

Defines the right process, voltage, and temperature (PVT) conditions to be used for timing analysis for a given design based on the product plans such as operating conditions and binning.

Collaborates with architecture, clocking design, and logic design teams to deliver flow development for chip integration and validates high performance low power clock network guidelines.

Familiar with Constraint Generation, development and clean up.

Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Prime Time based ECO flows.

Work on Automation scripts with in STA tools for Methodology development.

Familiar with digital design Implementation RTL to GDSII Synopsys/Cadence tools.

Familiar with LVF/POCV variation formats and understanding of deep sub-micron topics.

Participate in and lead cross-functional meetings to drive project progress and resolve timing-related challenges.

Act as a liaison between timing analysis and physical design teams, ensuring alignment and high-quality deliverables.

The ideal candidate should exhibit behavioral traits that indicate:

Self-motivator with strong problem-solving skills.

Excellent interpersonal skills, including written, verbal, and presentation communications.

Attention to detail and organizational skills.

Ability to work as part of a team and collaborate in a high-paced atmosphere.

Qualifications

Educational Qualifications:

BS/BTech degree with 8 years of experience, or MS/MTech degree with 6 years of experience in Electronics/VLSI/Computer Science or a related field.