Senior Design Verification Lead

As a Sub System Verification Lead Engineer at AMD, you will play a crucial role in verifying configurable switches and die-to-die interconnects as part of the Infinity Fabric transport layer verification team. With your expertise in System Verilog/UVM, you will be responsible for developing and enhancing testbenches for client, server, graphics, and semi-custom interconnects. Your collaboration with architects, RTL designers, and other team members will be essential in ensuring the excellence of the Infinity Fabric architecture. Additionally, you will mentor junior engineers to foster their growth and development in the field. Key Responsibilities: - Develop and enhance System Verilog / UVM-based testbenches for verifying new features - Collaborate with cross-functional teams to deepen expertise in Infinity Fabric architecture - Understand TestBench Architecture and develop proficiency in TestBench Verification Components - Mentor junior engineers to support their learning and skill development Preferred Experience: - Proficiency in IP or Sub-system level ASIC verification - Experience in developing complex verification environments and infrastructure - Exposure to scripting languages such as Perl, Ruby, Make, etc. - Familiarity with RTL design, software development, formal verification, or related domains - Prior experience in UVM TestBench Development for complex designs - Ideally, 15+ years of industry experience Academic Credentials: - Bachelors or masters degree in Electronics, Electrical, or Computer engineering Joining AMD means being part of a culture that thrives on innovation, collaboration, and inclusivity. At AMD, you will have the opportunity to work on cutting-edge technologies that shape the future of AI and beyond. Your contributions will be valued and recognized as we strive for execution excellence together. If you are passionate about pushing the limits of innovation and creating something extraordinary, AMD is the place for you. Shape your future with us!,