Senior Design Verification Engineering

Analog Devices

3 - 8 years

5 - 10 Lacs

bengaluru

Posted:2 days ago| Platform:

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Skills Required

semiconductor coding analytical analog soc ethernet debugging healthcare licensing uvm

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Work from Office

Job Type

Full Time

Job Description

Position: Senior Engineer, Digital Verification

Experience: Minimum 3 years

Requirements:

Extensive hands-on experience (3+ years) in digital verification using SystemVerilog (SV) and UVM methodology
Experience in developing verification plans for complex digital blocks
Experience in creating testbench environments at IP and/or Subsystem level
Experience in constrained random stimulus and coverage closure
Strong debugging skills and analytical problem-solving capabilities
Familiarity with ARM-AMBA protocols
Advantageous: Experience in formal verification and SystemVerilog Assertions (SV-Assertion) coding
Advantageous: Exposure to Ethernet standards

Responsibilities:

Develop comprehensive verification plans for complex digital modules at IP, Subsystem, and SoC levels
Design and implement reusable testbench components, including drivers, monitors, and scoreboards using SV-UVM
Work closely with design teams to achieve coverage closure
Coordinate with silicon test and evaluation teams to develop and deliver test patterns

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