Senior Design Verification Engineer-Barcelona

8 - 10 years

0 Lacs

india

Posted:2 weeks ago| Platform: Foundit logo

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Skills Required

simulation tools uvm systemverilog

Work Mode

On-site

Job Type

Full Time

Job Description

Senior Verification Engineer

Description

microprocessor architecture

What we offer

Requirements
  • Master or PhD
  • Industrial

    experience +8 years

  • Proficiency in

    SystemVerilog and UVM

  • Knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools
  • Experience with simulation and simulation tools
  • Knowledge of revision control methodology and tools (git, svn)
  • Experience in block level and sub-system or top level verification
  • Experience with formal and dynamic verification
  • Strong problem-solving skills and attention to detail

Excellent communication and teamwork abilities

#IndianEngineers #IndiaVerificationEngineer

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