Posted:1 month ago|
Platform:
Work from Office
Full Time
Owning the complete physical implementation process at both block and chip levels. Delivering timing clean blocks and chip-level designs that meet design targets. Ensuring DRC, LVS, and IR closure for all designs. Setting up and evaluating all aspects of the physical design flow, including place and route, timing, PV, and IR. Collaborating closely with the frontend design team to resolve design issues. Executing project responsibilities from start to completion, contributing to moderately complex aspects of the project. The Impact You Will Have: Ensuring the delivery of high-quality, timing-clean designs that meet industry standards. Driving innovation in physical design methodologies and processes. Contributing to the development of cutting-edge technologies that shape the future. Enhancing the overall efficiency and effectiveness of the design team. Providing mentorship and guidance to junior engineers, fostering a culture of continuous learning and improvement. Strengthening Synopsys position as a leader in the semiconductor industry through your expertise and contributions. What You ll Need: MSEE/BSEE with 6+ years of related experience in ASIC physical design. In-depth understanding of physical design specialization, with working knowledge of one other related area. Strong problem-solving skills and creativity in resolving design issues. Experience in scripting using Tcl and Perl. Ability to execute project responsibilities independently and contribute to team-driven projects. Who You Are: Detail-oriented and committed to delivering high-quality work. Collaborative and able to work effectively in a team environment. Proactive and able to take ownership of tasks and projects. Excellent communicator, capable of networking with senior personnel. Mentor and guide to junior peers, sharing knowledge and expertise.
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