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Renesas Electronics India Pvt. Ltd.
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Principal Verification Engineer - SoC/IP Design & Verification

Principal Verification Engineer - SoC/IP Design & Verification

Renesas Electronics India Pvt. Ltd.

10 - 15 years

25 - 30 Lacs

Hyderabad

Posted:2 months ago| Platform:

Apply

Skills Required

Automation Simulation Test strategy FPGA SOC Perl PCIE Firmware UVM Python

Work Mode

Work from Office

Job Type

Full Time

Job Description

We are seeking a

Principal Verification Engineer

to lead the functional verification of complex SoCs and IP blocks for next-generation high-performance computing (HPC), AI acceleration, and data center products. The ideal candidate will have deep experience in

SoC/IP functional verification

UVM/SystemVerilog

, and

coverage-driven methodologies

, with a strong focus on ensuring first-pass silicon success.

In this leadership role, you will drive

end-to-end verification strategy

, collaborate cross-functionally with architecture and design teams, and influence product definition through early design engagement.

Experience in Virtual Modeling, SystemC, and TLM

is a

strong plus

, enabling advanced verification flows and early software co-development.

Key Responsibilities

Verification Planning & Execution
- Own the definition and implementation of
  IP and SoC-level verification plans
  , including test strategy, coverage goals, and schedule.
- Develop
  UVM/SystemVerilog-based
  testbenches for complex IP and SoC subsystems, focusing on scalability, reuse, and maintainability.
- Lead
  coverage closure
  activities, including functional, code, and formal coverage, to ensure comprehensive verification.
Cross-Functional Collaboration
- Work closely with
  RTL designers, architects, firmware/software teams
  , and post-silicon validation to align on requirements and drive co-verification strategies.
- Participate in
  architecture and microarchitecture reviews
  , providing verification insights and influencing design for testability and verification efficiency.
Debug & Root Cause Analysis
- Perform advanced
  debug and root cause analysis
  of complex functional issues, collaborating with cross-disciplinary teams to drive resolutions.
- Utilize industry-standard tools for
  waveform analysis, simulation debug, and emulation/prototyping platforms
  .
Methodology & Process Improvement
- Define and drive best practices in
  verification methodology
  , including constrained-random testing, assertion-based verification, and coverage-driven approaches.
- Contribute to
  automation and regression flows
  , optimizing for quality and turnaround time.
Technical Leadership & Mentorship
- Mentor junior verification engineers, guide technical reviews, and contribute to team development and growth.
- Champion a culture of
  technical excellence, innovation, and continuous improvement
  .

Qualifications

Required Qualifications

Education & Experience
- B.S./M.S. in Electrical Engineering, Computer Engineering, or related discipline.
- 10+ years of hands-on experience
  in IP and/or SoC verification with a track record of successful silicon products.
Technical Expertise
- Proven expertise in
  UVM/SystemVerilog
  for developing scalable, reusable verification environments.
- Strong understanding of
  complex SoC designs
  , including
  memory controllers (DDR5, HBM3), PCIe, CXL
  , and high-speed interfaces.
- Experience with
  coverage-driven verification
  and closure techniques (functional, code, assertion coverage).
- Solid background in
  debugging RTL issues
  , simulation-based testing, and interaction with emulation/FPGA prototyping teams.
Verification Tools & Languages
- Proficient in
  simulation tools
  (VCS, Questa, Xcelium),
  waveform viewers
  , and scripting languages (
  Python, Perl, TCL
  ) for automation.
- Familiarity with
  formal verification tools
  and techniques is a plus.

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Principal Verification Engineer - SoC/IP Design & Verification

Experience & Salary

Skills Required

Work Mode

Job Type

Job Description

Principal Verification Engineer

SoC/IP functional verification

UVM/SystemVerilog

coverage-driven methodologies

end-to-end verification strategy

Experience in Virtual Modeling, SystemC, and TLM

strong plus

Key Responsibilities

Verification Planning & Execution

IP and SoC-level verification plans

UVM/SystemVerilog-based

coverage closure

Cross-Functional Collaboration

RTL designers, architects, firmware/software teams

architecture and microarchitecture reviews

Debug & Root Cause Analysis

debug and root cause analysis

waveform analysis, simulation debug, and emulation/prototyping platforms

Methodology & Process Improvement

verification methodology

automation and regression flows

Technical Leadership & Mentorship

technical excellence, innovation, and continuous improvement

Required Qualifications

Education & Experience

10+ years of hands-on experience

Technical Expertise

UVM/SystemVerilog

complex SoC designs

memory controllers (DDR5, HBM3), PCIe, CXL

coverage-driven verification

debugging RTL issues

Verification Tools & Languages

simulation tools

waveform viewers

Python, Perl, TCL

formal verification tools

More Jobs at Renesas Electronics India Pvt. Ltd.