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Western Digital
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Principal Engineer, Firmware Engineering- Low-level firmware, PCIe

Principal Engineer, Firmware Engineering- Low-level firmware, PCIe

Western Digital

7 - 12 years

40 - 45 Lacs

bengaluru

Posted:22 hours ago| Platform:

Apply

Skills Required

performance tuning system architecture c++ memory management hardware design pcie scheduling firmware

Work Mode

Work from Office

Job Type

Full Time

Job Description

We're looking for a highly accomplished and visionary

Principal Engineer

to lead the development of our NPU firmware runtime for the

Next Gen Computational Flash Controller

project. you'll be the technical owner of the device-side software stack that orchestrates all NPU operations. This is a rare opportunity to define the architecture of a high-performance compute platform, from kernel scheduling to data orchestration, at the deepest levels of the system.

Key Responsibilities

Architectural Leadership:
Serve as the technical lead for the entire NPU firmware runtime. you'll define the architecture for the communication and control plane that interacts with the host-side software stack via the PCIe driver.
Kernel Orchestration:
Design and implement the firmware for loading, scheduling, and executing kernels on the NPU. You will optimize the entire workflow from host command receipt to kernel launch, ensuring minimal latency and maximum throughput.
Data Flow and DMA Engine:
Architect the firmware responsible for managing high-bandwidth data flow. This includes interfacing with the
SRAM
to stage data and orchestrating the
DMA engine
to move data efficiently between the host, DRAM, and
High-Bandwidth Flash (HBF)
.
Performance Tuning:
Profile, analyze, and optimize the end-to-end performance of the NPU runtime. you'll identify bottlenecks at the firmware, hardware, and driver layers, and propose innovative solutions.
Cross-Functional Collaboration:
Work closely with the host-side software teams (PyTorch), hardware design teams, and silicon engineers to define APIs, debug complex issues, and ensure a seamless, high-performance solution.

Mentorship:

Act as a mentor and technical guide to other firmware and software engineers, fostering a culture of technical excellence and innovation

Experience:
7+ years of hands-on experience in low-level firmware or system software development.
Architectural Acumen:
Proven experience in defining the architecture of complex embedded or device-side systems.

Technical Expertise:

Mastery of C/C++
with a focus on writing high-performance, concurrent, and real-time code.
Deep understanding of system architecture, including
PCIe
, memory management, and DMA engines.
Experience with hardware bring-up, embedded processors, and on-chip peripherals.
Knowledge of deep learning frameworks (eg, PyTorch) and the underlying computation graphs.

Leadership Skills:
Demonstrated ability to lead complex technical projects and influence a diverse group of stakeholders without direct authority.
Problem-Solving:
Exceptional debugging and analytical skills, with a track record of solving the most challenging system-level problems.
Education:
Bachelors or Masters degree in Computer Science, Electrical Engineering, or a related field.

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San Jose CA

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Principal Engineer, Firmware Engineering- Low-level firmware, PCIe

Experience & Salary

Skills Required

Work Mode

Job Type

Job Description

Principal Engineer

Next Gen Computational Flash Controller

Key Responsibilities

Architectural Leadership:

Kernel Orchestration:

Data Flow and DMA Engine:

SRAM

DMA engine

High-Bandwidth Flash (HBF)

Performance Tuning:

Cross-Functional Collaboration:

Mentorship:

Experience:

Architectural Acumen:

Technical Expertise:

Mastery of C/C++

PCIe

Leadership Skills:

Problem-Solving:

Education:

More Jobs at Western Digital