11 Power Estimation Jobs

The ASIC Design Senior Engineer plays a critical role in the development and implementation of advanced integrated circuit designs within the organization. You will be instrumental in driving innovation and ensuring that the products maintain a competitive edge in the rapidly evolving semiconductor industry. Your responsibilities will include contributing technical expertise and leadership in the ASIC design process, from initial concept through to production. Working collaboratively with cross-functional teams, you will solve complex design challenges, optimize performance, and ensure adherence to industry standards. In addition to deep technical knowledge, this role will require the ability to mentor junior engineers and lead project initiatives. Your strong background in digital and analog design, along with a proven track record of delivering projects on time and within budget, will be essential in shaping the future of the technology solutions and impacting the company's success. Key Responsibilities: - Design and validate complex ASICs in accordance with specifications. - Develop RTL using Verilog/System Verilog for various digital components. - Conduct simulation and verification of designs using advanced methodologies. - Execute timing analysis and optimization to meet performance requirements. - Collaborate with cross-functional teams including hardware, software, and test engineering. - Perform power estimation and drive strategies for low-power design. - Oversee the transition from design to tape-out and ensure compliance with DFT standards. - Mentorship and training of junior engineers and interns in design practices. - Participate in design reviews and provide constructive feedback. - Address and resolve design-related issues throughout the lifecycle. - Communicate effectively with project managers to ensure timelines are met. - Document design processes and maintain accurate design records. - Utilize FPGA devices for prototyping and testing of ASIC functionalities. - Research and implement new design tools and methodologies. - Keep updated with industry trends and advancements in ASIC technology. Required Qualifications: - Bachelor's or Master's degree in Electrical Engineering or related field. - Minimum of 5 years of experience in ASIC design and development. - Strong experience with digital circuit design and verification methodologies. - Proficient in Verilog and System Verilog programming. - Hands-on experience with tools such as Cadence, Synopsys, and Mentor Graphics. - Familiarity with FPGA development and prototyping techniques. - Demonstrated experience in timing closure and power optimization. - Solid understanding of DFT concepts and techniques. - Ability to mentor junior engineers and lead design projects. - Excellent problem-solving and analytical skills. - Strong communication skills, both verbal and written. - Ability to work collaboratively in a fast-paced environment. - Knowledge of industry standards and best practices in ASIC design. - Experience with scripting languages such as Perl or Python is a plus. - Strong organizational skills and attention to detail. - Demonstrated track record of successful project delivery. Skills: system verilog, problem solving, simulation and verification, power optimization, DFT, timing analysis, schematic capture, FPGA development, low-power design, DFT standards, SoC, scripting languages (Perl, Python), Verilog, digital circuit design, RTL coding, ASIC design, power estimation.,

You will be responsible for developing and driving the Power Modelling and Estimation framework for highly optimized, modular, and scalable SoCs. Your main tasks will include working on power analysis, power optimization, simulation, and roll-ups. You should have hands-on experience with PTPX/Power artist and other industry standard power estimation tools. Additionally, you will collaborate with various SoC and IP teams on power projections and requirements, including silicon power capture and correlation with pre-si estimates. Data mining analysis at the RTL and gate-level to define relevant micro-architectural transactions for high-level power estimation will also be part of your responsibilities. Minimum qualifications for this position include a Bachelor's degree in Electrical Engineering, Computer Engineering, or a similar field, with at least 10 years of relevant work experience in consumer electronics or semiconductor companies. You should have a minimum of 5 years of experience with system design of small, medium, and large power management or power modeling systems, including hands-on experience with PTPX/Power artist tools. Preferred qualifications include a Bachelor's degree in Electrical Engineering, Computer Engineering, or a similar field, with at least 12 years of relevant work experience. You should have a strong ability to manage multiple projects, grow knowledge and capabilities of the power team, and perform hands-on testing. A background in analog or digital power design would be advantageous. This role falls under the Experienced Hire job type and will be based in India, Bangalore. The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms. CCG aims to deliver purposeful computing experiences that unlock people's potential. As part of the largest business unit at Intel, CCG is investing heavily in the PC, ramping its capabilities more aggressively, and designing the PC experience more deliberately to deliver a predictable cadence of leadership products. By joining this team, you will have the opportunity to fuel innovation across Intel and help enrich the lives of every person on earth. Please note that the work model for this role will be eligible for a hybrid work model, allowing employees to split their time between working on-site at the Intel site and off-site. Kindly be aware that job posting details such as work model, location, or time type are subject to change.,

Silicon Labs is the leading innovator in low-power wireless connectivity, dedicated to building embedded technology that connects devices and enhances lives. By incorporating cutting-edge technology into highly integrated SoCs, Silicon Labs empowers device manufacturers with the solutions, support, and ecosystems necessary for creating advanced edge connectivity applications. With operations in over 16 countries and headquartered in Austin, Texas, Silicon Labs is the trusted partner for innovative solutions in smart home, industrial IoT, and smart cities markets. Joining the team at Silicon Labs means being at the forefront of secure, intelligent wireless technology for a more connected world. As part of the team, you will play a critical role in defining platform requirements for scalable products targeting a wide range of IoT applications. Your responsibilities will include driving the architecture for a scalable compute platform, focusing on key technical areas such as core-compute architecture, high performance external memory interface, virtualization, isolation at SoC level, and more. To excel in this role, you will need to have a strong grasp of general SoC architecture, including boot, power management, clock & reset, debug & security. Experience in key architecture aspects like power estimation, die size estimation, and basic technology fundamentals will be crucial. You will be responsible for driving competitive analysis, product roadmaps, and ensuring clear mapping of the product portfolio to target applications. The ideal candidate will possess excellent communication skills to convey complex technical issues effectively and collaborate closely with cross-functional teams. You should be capable of translating high-level requirements into comprehensive product requirement documents and presenting technical overviews, competitive landscape analysis, and product positioning strategies. Minimum qualifications for this role include expertise in virtualization & isolation at the SoC level, a strong understanding of SoC architecture, experience in power estimation, and driving competitive analysis for product design and specifications. Additional qualifications such as full SoC flow know-how, hands-on experience in multiple functional areas, and business case analysis understanding will be considered a plus. As part of Silicon Labs, you will not only work with a highly skilled team where every engineer's contribution is valued, but you will also enjoy benefits such as Equity Rewards (RSUs), Employee Stock Purchase Plan (ESPP), insurance plans, National Pension Scheme (NPS), flexible work policies, childcare support, and a supportive work environment that promotes work-life balance and fun.,

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to create a smarter, connected future for all. As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. You should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 4+ years of Hardware Engineering experience, or a Master's degree with 3+ years of experience, or a PhD with 2+ years of experience. We are seeking bright ASIC design engineers with excellent analytical and technical skills to be part of a fast-paced team responsible for delivering Snapdragon CPU design for high-performance SoCs in sub-10nm process for Mobile, Compute, and IOT market space. In this role, you will participate in projects involved in the development of ASICs, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will create design experiments, perform detailed PPA comparison analysis, work closely with RTL design, Synthesis, low power, Thermal, Power analysis, and Power estimation teams to optimize Performance, Power, and Area (PPA). Key Responsibilities: - Develop Place & Route recipes for optimal PPA - Tabulate metrics results for analysis comparison - Complete ASIC flow with low power, performance, and area optimization techniques - Experience with STA using Primetime and/or Tempus - Proficient in constraint generation and validation - Knowledge of multiple power domain implementation with complex UPF/CPF definition - Formal verification experience (Formality/Conformal) - Skills in Perl/Tcl, Python, C++ - Strong problem-solving and ASIC development/debugging skills - Experience with CPU micro-architecture and their critical path - Low power implementation techniques experience - High-speed CPU implementation - Clock Tree Implementation Techniques for High Speed Design Implementation - Exposure to Constraint management tool and Verilog coding experience Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please email disability-accommodations@qualcomm.com or call Qualcomm's toll-free number. Qualcomm expects its employees to comply with all applicable policies and procedures, including security and confidentiality requirements. For more information about this role, please contact Qualcomm Careers.,

Qualcomm India Private Limited is seeking a passionate and skilled Hardware Engineer to join our Engineering Group. As a Hardware Engineer at Qualcomm, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include working on a wide range of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and deliver innovative solutions. To be considered for this role, you should hold a Bachelor's degree, Master's degree, or PhD in Computer Science, Electrical/Electronics Engineering, or a related field, along with 1-3+ years of Hardware Engineering experience. We are particularly interested in individuals with ASIC design expertise and strong analytical skills. This is a fantastic opportunity to contribute to the development of Snapdragon CPU design and high-performance SoCs in the Mobile, Compute, and IOT market space. Key responsibilities include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be required to conduct detailed analysis to improve results, optimize Performance, Power, and Area (PPA), and collaborate closely with various teams to achieve project goals. Proficiency in tools such as FC, Innovus, Primetime, Tempus, and languages like Perl, Tcl, Python, and C++ is highly desirable. Your role will involve developing Place & Route recipes for optimal PPA, managing constraints, and ensuring the implementation of low power techniques. Experience with CPU micro-architecture, clock tree implementation, Verilog coding, and formal verification will be valuable assets. Strong problem-solving skills and a dedication to ASIC development and debugging are essential in this role. Qualcomm is an equal opportunity employer committed to providing a supportive and accessible work environment for individuals with disabilities. If you require accommodations during the application process, please contact us at disability-accommodations@qualcomm.com. We expect all employees to adhere to company policies and procedures, including maintaining the confidentiality of proprietary information. Staffing and recruiting agencies are advised not to submit unsolicited profiles, applications, or resumes through our Careers Site. For further inquiries about this position, please reach out to Qualcomm Careers.,

Qualcomm India Private Limited is seeking an experienced professional to join their Engineering Group in the Hardware Engineering area. In this role, you will collaborate with cross-functional teams to work on System on Chip (SoC) Power and architecture for mobile SoC Application-Specific Integrated Circuits (ASICs). To be successful in this position, you should have a minimum of 4-12 years of experience in the following key areas: - Familiarity with low power intent concepts and languages such as UPF or CPF - Proficiency in power estimation and reduction tools like PowerArtist/PTPX and Calypto - Understanding of power dissipation and power savings techniques, including dynamic clock and voltage scaling - Competence in power analysis, covering leakage and dynamic aspects, as well as thermal impacts - Knowledge of power software features for power optimization - Experience with voltage regulators, including Buck and Low Drop out - Understanding of ASIC power grids and PCB Power Distribution Networks Additional skills that would be advantageous for this role include: - Familiarity with Mobile Baseband application processors chipset and power grid understanding - Experience with UPF-based synthesis and implementation using Design Compiler - Proficiency in structural low power verification tools like CLP or MVRC - Excellent written and verbal communication skills Some of the responsibilities associated with this role include: - Defining chip and macro level power domains - System Level Power Modeling - Mixed signal power analysis - Implementing Power Island/Power Gating/Power Isolation - Structural Low power design of level shifter and isolation cell topology and associated rules - Architectural analysis and development of digital power optimization logic/circuits/SW - Collaboration with Power Management IC developers for power grid planning - Creating detailed architecture and implementation documents Education Requirements: - Required: Bachelor's degree in Computer Engineering and/or Electrical Engineering - Preferred: Master's degree in Computer Engineering and/or Electrical Engineering Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 3+ years of Hardware Engineering or related work experience - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 2+ years of Hardware Engineering or related work experience - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 1+ year of Hardware Engineering or related work experience Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations to individuals with disabilities during the application/hiring process. If you require an accommodation, you may contact disability-accommodations@qualcomm.com. It is crucial for all employees at Qualcomm to adhere to applicable policies and procedures, including those related to the protection of confidential information. Please note that Qualcomm's Careers Site is intended for individuals seeking job opportunities directly with Qualcomm. Staffing and recruiting agencies, as well as individuals being represented by agencies, are not permitted to submit profiles, applications, or resumes through this site. For further information on this role, please reach out to Qualcomm Careers.,

As a Senior Silicon Design Engineer at AMD, you will play a key role in contributing to the development and verification of cutting-edge technologies that drive innovation in the computing industry. Your passion for modern processor architecture, digital design, and verification will be instrumental in ensuring the highest quality products are delivered to the market. In this role, you will collaborate with a diverse team of engineers to implement front-end designs from RTL to netlist, conduct formal verification checks, and debug any timing, area, or congestion issues that may arise. Your ability to analyze inter-block timing and develop timing constraints will be crucial in optimizing the performance of the designs. Key responsibilities include running logic/physical synthesis, performing power estimation, and developing automation scripts for various front-end tools. Your strong analytical and problem-solving skills will be essential in identifying and addressing potential design issues, as well as working closely with architects, RTL designers, and SOC teams to ensure efficient IP quality. To excel in this role, you should have 5 to 10 years of experience in front-end implementation, familiarity with power analysis, and a background in computing/graphics. A Bachelor's or Master's degree in computer engineering or electrical engineering is required to be successful in this position. Join us at AMD and be part of a team that is dedicated to pushing the limits of innovation and solving the world's most important challenges. Together, we advance towards a future where technology enriches lives and transforms industries.,

Qualcomm India Private Limited is a leading technology innovator that strives to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. This involves working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and develop innovative solutions. To qualify for this position, you should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field along with 4+ years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years or a PhD with 2+ years of relevant work experience would be considered. We are seeking bright ASIC design engineers with strong analytical and technical skills to be part of a dynamic team responsible for delivering Snapdragon CPU design for Mobile, Compute, and IOT markets. Key responsibilities include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be involved in creating design experiments, conducting PPA comparison analysis, and collaborating closely with RTL design, Synthesis, low power, Thermal, Power analysis, and Power estimation teams to optimize Performance, Power, and Area (PPA). Additionally, developing Place & Route recipes for optimal PPA, tabulating metrics results for analysis, and contributing to the ASIC flow with low power, performance, and area optimization techniques are crucial aspects of this role. The ideal candidate should have 10-15 years of High-Performance core Place & Route and ASIC design Implementation work experience. Proficiency in Place & Route with FC or Innovus, experience with STA using Primetime and/or Tempus, and strong problem-solving skills are preferred qualifications. Knowledge in constraint generation and validation, power domain implementation, formal verification, scripting languages like Perl/Tcl, Python, C++, as well as exposure to Verilog coding and CPU micro-architecture will be advantageous. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. The company's work environment is inclusive and supportive of individuals with disabilities. Applicants should adhere to all relevant policies and procedures, including security measures and confidentiality of company information. Qualcomm does not accept unsolicited resumes or applications from staffing agencies. For more information about this role, please reach out to Qualcomm Careers.,

THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD's graphics processor IP, resulting in no bugs in the final design.?? THE PERSON: ? You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: ? Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues? Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: ? required to be experienced in powerestimation, analysis, optimization experience with tools PTPX/Power Artist physical design experience with ICC/Innovus, and saif based power optimization is a plus front end design knowledge data paths understanding, reviewing waveforms etc,. is a plus knowledge of power management methodologies (including clock gating, power gating, voltage frequency scaling, etc...) is a plus Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools? Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++?? Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributedcomputeenvironment.?? Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts andSystemVeriloglanguage Good working knowledge ofSystemCand TLM with some related experience.?? Scripting language experience: Perl, Ruby,Makefile, shell preferred.?? Exposure to leadership or mentorship is an asset Desirableassetswith prior exposure to video codec system or other multimedia solutions.?? ACADEMIC CREDENTIALS: ? Bachelors orMastersdegree in computer engineering/Electrical Engineering

THE ROLE: The focus of this role is to plan, build, and execute thePower analysis and optimizationof new and existing features for AMD's APU, resulting in no bugs in the final design.?? THE PERSON: ? You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. ? KEY RESPONSIBILITIES: ? Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues? Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: ? required to be experienced in powerestimation, analysis, optimization experience with tools PTPX/Power Artist physical design experience with ICC/Innovus, and saif based power optimization is a plus front end design knowledge data paths understanding, reviewing waveforms etc,. is a plus knowledge of power management methodologies (including clock gating, power gating, voltage frequency scaling, etc...) is a plus Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools? Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++?? Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributedcomputeenvironment.?? Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts andSystemVeriloglanguage Good working knowledge ofSystemCand TLM with some related experience.?? Scripting language experience: Perl, Ruby,Makefile, shell preferred.?? Exposure to leadership or mentorship is an asset Desirableassetswith prior exposure to video codec system or other multimedia solutions.??

Qualcomm India Private Limited is a leading technology innovator that aims to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, test systems, FPGA, and/or DSP systems to launch cutting-edge products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. To be considered for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field along with 4+ years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years of experience or a PhD with 2+ years of experience is also acceptable. The ideal candidate should possess strong analytical and technical skills, especially in ASIC design. Responsibilities for this position include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be expected to create design experiments, conduct detailed PPA comparison analysis, collaborate with various teams for optimization, and develop Place & Route recipes for optimal PPA results. Qualifications required for this role include 6-15 years of experience in High-Performance core Place & Route and ASIC design Implementation. Preferred qualifications involve extensive experience in Place & Route with FC or Innovus, knowledge of complete ASIC flow with optimization techniques, proficiency in STA using Primetime and/or Tempus, and skills in Perl/Tcl, Python, C++, among others. Problem-solving abilities, experience with CPU micro-architecture, low power implementation techniques, and clock tree implementation techniques are also desired. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If accommodation is needed during the application/hiring process, individuals can contact Qualcomm for support. The company expects its employees to adhere to all applicable policies and procedures, including confidentiality requirements. Staffing and recruiting agencies are advised that only individuals seeking a job at Qualcomm should use the Careers Site. Unsolicited submissions from agencies will not be accepted. For more information about this role, interested individuals can contact Qualcomm Careers directly.,