Physical Design Engineer III, Silicon

As a member of the team at Google, you will be involved in developing custom silicon solutions for Google's direct-to-consumer products. Your contribution will help in shaping the future hardware experiences, focusing on performance, efficiency, and integration. The Platforms and Devices team at Google is responsible for various computing software platforms and first-party devices that incorporate Google AI, software, and hardware, aiming to create innovative experiences for users globally. **Key Responsibilities:** - Use investigative and simulation techniques to ensure Performance, Power, and Area (PPA) meet defined requirements. - Collaborate with cross-functional teams to debug failures or performance shortfalls and make necessary adjustments. - Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route to ensure alignment with power, performance, and area goals. - Develop, validate, and enhance Electronic Design Automation (EDA) methodology for a specialized sign-off or implementation domain to facilitate cross-functional teams in building and delivering rectified blocks. **Qualifications Required:** - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience. - 4 years of experience with programming languages like Perl, Python, or TCL. - Experience in managing block physical implementation and Quality of Results (QoR). - Experience with ASIC Register-Transfer Level to Graphic Data System (RTL to GDS) implementation for high PPA designs. **Preferred Qualifications:** - Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with a focus on computer architecture. - Experience with constraints, synthesis, or Clock Tree Synthesis (CTS). - Experience with 7/5/3/2nm node technology. - Knowledge of RTL to GDSII in innovus or cadence tools. - Familiarity with Electromigration IR Drop (EMIR), Static Timing Analysis (STA), Photon Doppler Velocimetry (PDV), Logic Equivalence Check (LEC), and VC Low Power (VCLP) flows.,