Physical Design and Timing Engineer, Signoff Methodology

As a Physical Design Engineer at Google, you will play a crucial role in developing custom silicon solutions that drive the future of Google's consumer products. Your work will contribute to the innovation behind widely loved products, shaping the next generation of hardware experiences with a focus on performance, efficiency, and integration. With a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, along with 5 years of experience in timing analysis and physical design, you will bring a solid foundation to the team. Additionally, experience in scripting languages such as Perl, TCL, Python is required. Your responsibilities will include driving physical design and sign-off timing methodologies for mobile System on a Chips (SoC) to optimize Power Performance Area (PPA) and yield. You will analyze power performance area trade-offs and collaborate with cross-functional teams including architecture, IPs, design, foundry, CAD, and sign-off methodology teams. Preferred qualifications include experience in physical design tool automation, extraction of design parameters, and knowledge of parasitic extraction tools and flow. You will also be expected to have knowledge of timing signoff conditions and parameters. Join our team at Google, where we strive to make the world's information universally accessible and useful through the integration of AI, software, and hardware. Be a part of our mission to create technologies that enhance people's lives and make computing faster, seamless, and more powerful.,