8.0 - 13.0 years

15 - 30 Lacs

Hyderabad

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Experience: 8+ Years Location: Hyderabad Notice Period: Immediate to 15 Days Required Expertise: Deep understanding of Linux kernel internals, especially drivers/pci and subsystems like hotplug, MSI, IOMMU, DMA API. Hands-on experience with PCIe Gen3/Gen4/Gen5 devices and related PHY bring-up issues. Familiarity with ARM64 and x86 architectures, DT/ACPI handling for PCI devices. Proficient in C programming, Linux kernel debugging (GDB, crash dumps), and tools like dmesg, lspci, pcie_check. Expertise in power management (runtime, suspend/resume flows) for PCI devices. Experience with Secure Boot, TrustZone, and virtualization passthrough (VFIO/SR-IOV) for PCIe devices is a strong plus. Experience using Yocto, Buildroot, or other embedded Linux build systems.

Posted 4 weeks ago

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Ams Verification Engineer Intverse It Solutions

4.0 - 8.0 years

15 - 20 Lacs

Bengaluru

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Key Responsibilities Architect and implement System Verilog/UVM-based testbenches and verification environments for analogmixed signal blocks and SoCs. Develop VerilogA , RealNumber Models (RNM) , WREAL models, and support cosimulation with SPICE for behavioral accuracy. Execute verification of highspeed serial protocols including PCIe , USB 3 , MIPI CSI/DSI , using constrainedrandom stimulus, assertions, monitors, functional coverage. Utilize tools like PrimeSim XA (VCS AMS) to run mixed-signal regressions and VerilogA analog simulations. Collaborate closely with digital, analog, synthesis, timing, and silicon bring-up teams to ensure spec traceability, debug failures, and validate first-pass silicon performance. Write thorough verification plans , track coverage closure, debug RTL/AMS models, document results, and drive continuous improvement of methodologies. Qualifications & Skills Bachelors/Masters in Electronics/Telecommunication, Computers, Electrical . 5+ years of mixed-signal/AMS verification experience; SoC-level IP/subsystem/SoC verification preferred. Deep proficiency in System Verilog , UVM , assertions, functional coverage, OOP testbench design. Strong expertise in VerilogA , RNM/WREAL , and building analog behavioral models Simply. Hands-on experience with PrimeSim XA/VCS AMS , Cadence Spectre/Xcelium, Synopsys AMS toolchains.

Posted 1 month ago

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