Silicon Design Verification Manager II, Camera ISP Google

4.0 - 10.0 years

0 Lacs

karnataka

On-site

As a successful candidate for this role, you should possess a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or have equivalent practical experience. You should have at least 10 years of experience in Camera ISP image processing or other multimedia IPs like Display or Video Codec. Additionally, you should have a solid background with System Verilog Assertions (SVA), assertion-based verification, and formal verification, with at least 4 years of experience in people management and employee development. Preferred qualifications for this position include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, focusing on computer architecture. It would be advantageous to have experience in low-power design verification, working with RTL design and integration teams to enhance team productivity and velocity, and collaborating with software teams to define hardware/software interfacing. Join our team that is dedicated to pushing boundaries and creating custom silicon solutions to drive Google's direct-to-consumer products into the future. You will play a crucial role in innovating products that are beloved by people worldwide, shaping the next generation of hardware experiences with superior performance, efficiency, and integration. As part of our mission to organize the world's information and make it universally accessible and useful, we combine the expertise of Google AI, Software, and Hardware to develop groundbreaking technologies. Our goal is to make computing faster, seamless, and more powerful, ultimately enhancing people's lives through technology. In this role, your responsibilities will include leading a team of individuals, setting and communicating individual and team priorities aligned with organizational goals, providing regular performance feedback and coaching, collaborating cross-functionally to debug failures and ensure design functional correctness, devising test plans and verification strategies, planning the verification of complex Camera ISP hardware IPs, and creating advanced verification environments using System Verilog and UVM. If you are passionate about driving innovation, working on cutting-edge technologies, and contributing to the advancement of hardware experiences, we invite you to join us on this exciting journey.,

Posted 1 week ago

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2.0 - 6.0 years

0 Lacs

karnataka

On-site

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 2 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, and low-power design techniques. Experience with a scripting language such as Perl or Python. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience. Experience implementing image/video processing blocks or other multimedia IPs such as Display or ISP Experience with Application-Specific Integrated Circuit (ASIC) design methodologies for clock domain checks and reset checks Experience in scripting languages, C/C++ programming and software design skills. About the job Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be responsible for Register-Transfer Level (RTL) design development of security IP and subsystems. This includes Micro architecture, RTL coding, definition, constraints, IP release flows, Power Performance Area (PPA) optimizations, test planning collaboration, coverage reviews and closure for quality and optimized security designs. You will be involved in Micro-Arch and RTL coding for imaging and video codecs - IPs and subsystems. You will also contribute to improvements by debugging and by using different RTL QC tools like Lint, CDC, VCLP. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Perform Verilog/SystemVerilog RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks. Perform RTL verification using industry standard methodologies. Participate in test planning and coverage analysis. Develop RTL implementations that meet competitive power, performance and area targets. Participate in synthesis, timing/power closure and Field-Programmable Gate Array (FPGA) or silicon bring-up. Work with multi-disciplined and multi-site teams in RTL design, verification, or architecture or micro-architecture planning. ,

Posted 2 weeks ago

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