Mask Designer

You are seeking a Digital/Memory Mask Design Engineer to join a dynamic team managing complex high-speed digital memory circuit designs at NVIDIA. As a part of the team, you will be involved in reinventing the field of artificial intelligence and enhancing human creativity and intelligence. You will work in a diverse and supportive environment where delivering your best work is encouraged. Your responsibilities will include: - Executing IC layout for innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes of 3nm, 5nm, 7nm, and lower nodes using industry-standard methodologies. - Leading the architecture and layout design of critical memory subsystems, such as control logic, sense amplifiers, I/O blocks, bit-cell arrays, and decoders for advanced technology nodes. - Overseeing custom layout and verification of complex memory cells, establishing standards and methodologies for compiler-driven design flows. - Managing and optimizing all physical verification activities, including DRC, LVS, density analysis, and comprehensive tape-out checks. - Identifying and resolving intricate physical design issues in compiler-generated layouts, while mentoring junior engineers in established methodologies. - Providing expertise on IR drop and EM mitigation strategies, creating design methodologies for resilient memory layouts. - Demonstrating deep knowledge in ultra-deep sub-micron layout challenges, regularly introducing and implementing advanced solutions. - Developing memory compilers, leading problem-solving efforts, and driving optimization for performance, area, and manufacturability. - Fostering effective teamwork across cross-functional teams, influencing project direction and ensuring alignment with organizational goals. - Excelling in resource management, representing the team in technical discussions with customers. - The layout of IP will feature significant digital components. - Embracing and implementing the best layout practices/methodology for composing digital Memory layouts. - Adhering to company procedures and practices for IC layout activities. Desired qualifications: - B.E/B Tech. / M Tech in Electronics or equivalent experience with a minimum of 2 years" proven expertise in Memory layout in advanced CMOS processes. - Proficiency in industry-standard EDA tools for Cadence. - Experience in laying out high-performance memories of various types. - Knowledge of Layout fundamentals, including different bit cells, Decoders, LIO, etc. (matching devices, symmetrical layout, signal shielding). - Experience with floor planning, block-level routing, and macro-level assembly. - Profound understanding of top-level verification, including EM/IR quality checks, and detailed knowledge of layout-dependent effects such as LOD, Dummification, fills, etc.,