Lead Engineer, Analog Mixed Signal Layout

Role Overview: You should have 8-10 years of work expertise in the field. You will be responsible for designing high performance analog layouts in advance CMOS process nodes. Your expertise in layouts of high performance and high-speed analog blocks such as ADC, DAC, PLL is required. High speed SERDES expertise is mandatory for this role. You should be well-versed in analog layout techniques like common centroid, interdigitation, shielding, dummy devices, EM aware routing on critical block, and must be familiar with VXL compliant methodology. Additionally, you will be responsible for physical verification checks including DRC, LVS, DFM, ERC, EM, IR, etc. Knowledge of layout automation using SKILL/PERL/Python will be an added advantage. Key Responsibilities: - Design high performance analog layouts in advance CMOS process nodes - Layouts of high performance and high-speed analog blocks such as ADC, DAC, PLL - Design high speed SERDES - Implement analog layout techniques like common centroid, interdigitation, shielding, dummy devices, EM aware routing on critical block - Conduct physical verification checks including DRC, LVS, DFM, ERC, EM, IR - Automate layout using SKILL/PERL/Python Qualifications Required: - B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Engineering Note: No additional details of the company were mentioned in the provided job description. Role Overview: You should have 8-10 years of work expertise in the field. You will be responsible for designing high performance analog layouts in advance CMOS process nodes. Your expertise in layouts of high performance and high-speed analog blocks such as ADC, DAC, PLL is required. High speed SERDES expertise is mandatory for this role. You should be well-versed in analog layout techniques like common centroid, interdigitation, shielding, dummy devices, EM aware routing on critical block, and must be familiar with VXL compliant methodology. Additionally, you will be responsible for physical verification checks including DRC, LVS, DFM, ERC, EM, IR, etc. Knowledge of layout automation using SKILL/PERL/Python will be an added advantage. Key Responsibilities: - Design high performance analog layouts in advance CMOS process nodes - Layouts of high performance and high-speed analog blocks such as ADC, DAC, PLL - Design high speed SERDES - Implement analog layout techniques like common centroid, interdigitation, shielding, dummy devices, EM aware routing on critical block - Conduct physical verification checks including DRC, LVS, DFM, ERC, EM, IR - Automate layout using SKILL/PERL/Python Qualifications Required: - B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Engineering Note: No additional details of the company were mentioned in the provided job description.