IC Package Design Eng

HCLTech

5 - 10 years

8 - 18 Lacs

bengaluru

Posted:6 days ago| Platform:

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Skills Required

allegro apd mentor graphics cadence allegro allegro design flipchip

Work Mode

Work from Office

Job Type

Full Time

Job Description

Role & responsibilities

IC Package Layout Design Engineer
Experience with IC Package Layout Design using Cadence Allegro APD (will consider Mentor Graphics XPD, XSI tools experience also)
Good understanding of package/substrate design and package assembly rules related to flip chip designs.
Exposure to different package technologies such as MCM, flip chip / wire bond, 3D, 2.5D etc., added advantage.
Expertise in High-Speed Complex PCB and Package designs with HDI, Blind and Buried Via technologies.
Hands-on expertise with PCB and Package layout designs involving High Speed Parallel Bus interfaces including DDR, GDDR and HSIO interfaces including PCIe, SERDES and Type C.
Good Exposure to Stackup design, substrate DFM, DFA rules and adherence.
Should have expertise in constraint setting in layout tool.

Preferred candidate profile

Experinec in IC Package Layout Design, Substrate Design, Flip Chip, Wire bond, Cadence APD (Primary), Mentor Graphics Expedition (Secondary). Cadence APD is Primary tool

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