Posted:2 weeks ago|
Platform:
Hybrid
Full Time
Perform verification for high-speed FPGA digital design using UVM/OVM for complex mathematical and control logic algorithms. Developing Verilog/VHDL code. Full testing of FPGA design which include testing of complete design with PS.
Anjanaire Technologies
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Bengaluru
9.0 - 13.0 Lacs P.A.
Mumbai, Maharashtra, India
3.0 - 6.0 Lacs P.A.
Delhi, Delhi, India
3.0 - 6.0 Lacs P.A.
Kolkata, West Bengal, India
3.0 - 6.0 Lacs P.A.
Bengaluru / Bangalore, Karnataka, India
3.0 - 6.0 Lacs P.A.
6.0 - 16.0 Lacs P.A.
Chennai, Pune, Delhi, Mumbai, Bengaluru, Hyderabad, Kolkata
5.0 - 8.0 Lacs P.A.
Bengaluru
9.0 - 13.0 Lacs P.A.
5.0 - 8.0 Lacs P.A.
5.0 - 8.0 Lacs P.A.