EDA Engineer (Timing Analysis)

2 - 5 years

10 - 20 Lacs

Posted:8 hours ago| Platform: Naukri logo

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Job Type

Full Time

Job Description

Role:

What they do:

  • Analyze design issues in

    Vivado

    implementation flow.
  • Apply and debug

    timing constraints

    to ensure design closure.
  • Propose/design corrections to fix issues.
  • Use

    scripting (Shell/Python/TCL)

    to automate and improve analysis.
  • (RTL/Verilog knowledge is optional, not mandatory.)

Mandatory Skills:

  • Strong in

    Timing Constraints (STA concepts)

  • Hands-on with

    Vivado tool flow

  • Shell/Python/TCL scripting

    for automation

Good to have:

  • Quartus exposure
  • Basic RTL/Verilog understanding

timing + Vivado design analysis

Feel free to share the resume if you feel its a good fit

svishnuraj@teksystems.com

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