Digital IC Design Principal Engineer

As a Digital IC Design Principal Engineer with Marvell, you ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You ll be part of a digital team of about eight people making a big impact on this organization, working on ultra-dense and performance Static Random Access Memory (SRAM) memory compilers.
This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates. As a Principal Design Engineer, you will lead micro-architecture and RTL development and HW/SW co-design efforts working across multi-functional teams, in developing state-of-the-art designs for the up and coming CXL product roadmap. Additional responsibilities will include, but not be limited to: Responsible for micro-architecture design and development of SOC and associated component IP like Memory Controllers/PCIE interface/CXL interfaces etc. Working with Architects and Verification engineers to deliver develop complex, high performance and timing critical designs through all aspects of the SoC front-end design flow (incl. timing closure and power optimization) Bachelor s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience. Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience. Strong understanding of SoC architecture, processor cores, memory and peripheral interfaces through hands on prior experience. Extensive experience in Verilog/VHDL, Spyglass and Quality checks of the implemented RTL for LINT, CDC. Hands on experience in interpretive language such as Perl/Python. Proven track record of delivering production-quality designs on aggressive development schedules. Domain expertise in CXL/PCIe protocols, DDR memory controllers is a plus. #LI-CP1