Design Verification Technical Manager

20 years

0 Lacs

Posted:2 weeks ago| Platform: Linkedin logo

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Work Mode

On-site

Job Type

Full Time

Job Description

Experience Level: 20+ years of industry exp, with at least 5+ years in team management


Key Responsibilities:

We are hiring for candidate needs to have a hands-on experience with SV, UVM. Should have exposure to different verification methodologies and flows at IP, Sub System or SoC Level. Power Aware verification exposure, GLS verification exp is a plus. Lead and manage a team of highly motivated design verification engineers, providing technical guidance, mentorship and team management.

Qualifications & Experience:

  • Bachelor's / Master's degree in Electrical/Electronics/Instrumentation/Computer Engineering, or related fields from an institute of repute.
  • 20+ years of industry experience.
  • Strong hands-on experience in TB design, test plan creation. Proficiency in verification flows, methodologies and languages such as System Verilog & UVM.

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