Design Verification HBM Protocol

Job Title: Design Verification Engineer HBM / Memory Controller

Location:

Experience:

Role Overview

Design Verification Engineer

Key Responsibilities

1. Functional & Performance Validation Memory Controller (HBM)

• End-to-end

  functional and performance validation

  of HBM-based memory controller IP/Sub-system.
• Development of

  test content

  for both functional and performance scenarios.
• Execution of test plans, test runs, waveform debug, and issue isolation.
• Handling

  regression setup

  , tracking failures, triaging issues, and driving closure.

• Coverage planning, coding, reporting, and analysis

  (Functional & Code Coverage).
• Root-cause analysis and collaboration with RTL, architecture, and firmware teams for bug resolution.

Required Technical Skills

? HBM / Memory Expertise

• Strong hands-on experience with

  HBM (HBM2 / HBM2E / HBM3)

  protocols.
• Understanding of memory controller architecture, DFI, PHY interactions.
• Experience verifying high-speed memory interfaces.

? Design Verification Mandatory

• Solid experience in

  SystemVerilog

  for DV.
• Expertise in

  UVM Verification methodology

  .
• Testbench architecture, stimulus generation, scoreboard, functional coverage.
• Experience with

  Assertion-Based Verification (SVA)

  .

? Debug & Analysis

• Strong debugging using waveforms (e.g., Simvision, DVE, Verdi).
• Failure triaging and RCA for functional and performance issues.
• Regression execution and debug in simulation environments.

? Tools & Simulators

Experience with industry-standard verification tools:

• Synopsys

  : VCS, Verdi

• Cadence

  : Incisive/Xcelium, Simvision

• Mentor/Siemens

  : Questa/Modelsim
• Coverage tools, code coverage, functional coverage, assertion coverage.